STM32F10xx4 STM32F10xx6 Errata sheet

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Contents STM32F10xx4 STM32F10xx6,1 Arm 32 bit Cortex M3 limitations 6. 1 1 Cortex M3 limitations description for STM32F10xx4 6. low density devices 7, 1 1 1 Cortex M3 LDRD with base in list may result in incorrect base register. when interrupted or faulted 7, 1 1 2 Cortex M3 event register is not set by interrupts and debug 7. 1 1 3 Cortex M3 BKPT in debug monitor mode can cause DFSR mismatch 7. 1 1 4 Cortex M3 may freeze for SLEEPONEXIT single instruction ISR 8. 1 1 5 Interrupted loads to SP can cause erroneous behavior 8. 1 1 6 SVC and BusFault MemManage may occur out of order 9. 2 STM32F101x4 6 STM32F102x4 6 and STM32F103x4 6,silicon limitations 10. 2 1 Voltage glitch on ADC input 0 12, 2 2 Flash memory read after WFI WFE instruction 12.
2 3 Debug registers cannot be read by user software 12. 2 4 Debugging Stop mode and system tick timer 13,2 5 Debugging Stop mode with WFE entry 13. 2 6 Wakeup sequence from Standby mode when using more. than one wakeup source 13,2 7 LSE start up in harsh environments 14. 2 8 RDP protection 14,2 9 Alternate functions 15,2 9 1 USART1 RTS and CAN TX 15. 2 9 2 SPI1 in slave mode and USART2 in synchronous mode 15. 2 9 3 SPI1 in master mode and USART2 in synchronous mode 16. 2 9 4 I2C with SPI remapped and used in master mode 16. 2 9 5 I2C1 and TIM3 CH2 remapped 16,2 9 6 USARTx TX pin usage 17. 2 10 PVD and USB wakeup events 18, 2 11 Boundary scan TAP wrong pattern sent out after the.
capture IR state 18, 2 12 Flash memory BSY bit delay versus STRT bit setting 18. 2 13 I2C peripheral 19,2 35 ES0348 Rev 9,STM32F10xx4 STM32F10xx6 Contents. 2 13 1 Some software events must be managed before the current byte is. being transferred 19,2 13 2 Wrong data read into data register 20. 2 13 3 SMBus standard not fully supported 21, 2 13 4 Wrong behavior of I2C peripheral in master mode after a. misplaced Stop 21, 2 13 5 Mismatch on the Setup time for a repeated Start condition timing.
parameter 22, 2 13 6 Data valid time tVD DAT violated without the OVR flag being set 22. 2 13 7 I2C analog filter may provide wrong value locking BUSY flag and. preventing master mode entry 23,2 14 SPI peripheral 25. 2 14 1 CRC still sensitive to communication clock when SPI is in slave mode. even with NSS high 25, 2 14 2 SPI CRC may be corrupted when a peripheral connected to the same. DMA channel of the SPI is under DMA transaction close to the end of. transfer or end of transfer 1 25,2 15 USART peripheral 26. 2 15 1 Parity Error flag PE is set again after having been cleared. by software 26, 2 15 2 Idle frame is not detected if receiver clock speed is deviated 26.
2 15 3 In full duplex mode the Parity Error PE flag can be cleared by. writing the data register 26, 2 15 4 Parity Error PE flag is not set when receiving in Mute mode using. address mark detection 27, 2 15 5 Break frame is transmitted regardless of nCTS input line status 27. 2 15 6 nRTS signal abnormally driven low after a protocol violation 27. 2 16 Timers 28,2 16 1 Missing capture flag 28,2 16 2 Overcapture detected too early 28. 2 16 3 General purpose timer regulation for 100 PWM 28. 2 17 LSI clock stabilization time 29,2 18 USB packet buffer memory over underrun or. COUNTn RX 9 0 field reporting incorrect number if APB1. frequency is below 13 MHz 29,Appendix A Revision code on device marking 30.
Revision history 33,ES0348 Rev 9 3 35,List of tables STM32F10xx4 STM32F10xx6. List of tables,Table 1 Device Identification 1,Table 2 Device summary 1. Table 3 Cortex M3 core limitations and impact on microcontroller behavior 6. Table 4 Summary of silicon limitations 10,Table 5 Document revision history 33. 4 35 ES0348 Rev 9,STM32F10xx4 STM32F10xx6 List of figures. List of figures, Figure 1 LSE start up using an additional resistor 14.
Figure 2 LQFP64 package top view 30,Figure 3 LQFP48 package top view 31. Figure 4 VFQFPN36 package top view 32,ES0348 Rev 9 5 35. Arm 32 bit Cortex M3 limitations STM32F10xx4 STM32F10xx6. 1 Arm 32 bit Cortex M3 limitations, An errata notice for the Arm a STM32F10xx4 6 core revisions r0 is available from. http infocenter arm com, All the described limitations are minor and related to the revision r1p1 01rel0 of the. Cortex M3 core Table 3 summarizes these limitations and their implications on the behavior. of low density STM32F10xx4 6 devices, Table 3 Cortex M3 core limitations and impact on microcontroller behavior.
Arm Arm Impact on low density,category summary of errata STM32F10xx4 6 devices. Interrupted loads to SP can cause erroneous,752419 Cat 2 Minor. SVC and BusFault MemManage may occur out of,740455 Cat 2 Minor. LDRD with base in list may result in incorrect base. 602117 Cat 2 Minor,register when interrupted or faulted. 563915 Cat 2 Event register is not set by interrupts and debug Minor. 531064 impl SWJ DP missing POR reset sync No,Cortex M3 may fetch instructions using incorrect.
511864 Cat 3 No,privilege on return from an exception. 532314 Cat 3 DWT CPI counter increments during sleep No. 538714 Cat 3 Cortex M3 TPIU clock domain crossing No. 548721 Cat 3 Internal write buffer could be active whilst asleep No. BKPT in debug monitor mode can cause DFSR,463763 Cat 3 Minor. Core may freeze for SLEEPONEXIT single,463764 Cat 3 Minor. instruction ISR,Unaligned MPU fault during a write may cause the. 463769 Cat 3 wrong data to be written to a successful first No. a Arm is a registered trademark of Arm Limited or its subsidiaries in the US and or elsewhere. 6 35 ES0348 Rev 9, STM32F10xx4 STM32F10xx6 Arm 32 bit Cortex M3 limitations.
1 1 Cortex M3 limitations description for STM32F10xx4 6. low density devices, Only the limitations described below have an impact though minor on the implementation. of STM32F10xx4 6 low density devices, All the other limitations described in the Arm errata notice and summarized in Table 3. above have no impact and are not related to the implementation of STM32F10xx4 6 low. density devices Cortex M3 r1p1 01rel0, 1 1 1 Cortex M3 LDRD with base in list may result in incorrect base register. when interrupted or faulted,Description, The Cortex M3 Core has a limitation when executing an LDRD instruction from the system. bus area with the base register in a list of the form LDRD Ra Rb Ra imm The. execution may not complete after loading the first destination register due to an interrupt. before the second loading completes or due to the second loading getting a bus fault. Workarounds, 1 This limitation does not impact the STM32F10xx4 6 code execution when executing.
from the embedded Flash memory which is the standard use of the microcontroller. 2 Use the latest compiler releases As of today they no longer generate this particular. sequence Moreover a scanning tool is provided to detect this sequence on previous. releases refer to your preferred compiler provider. 1 1 2 Cortex M3 event register is not set by interrupts and debug. Description, When interrupts related to a WFE occur before the WFE is executed the event register. used for WFE wakeup events is not set and the event is missed Therefore when the WFE. is executed the core does not wake up from WFE if no other event or interrupt occur. Workaround, Use STM32F10xx4 6 external events instead of interrupts to wake up the core from WFE by. configuring an external or internal EXTI line in event mode. 1 1 3 Cortex M3 BKPT in debug monitor mode can cause DFSR mismatch. Description, A BKPT may be executed in debug monitor mode This causes the debug monitor handler. to be run However the bit 1 in the Debug fault status register DFSR at address. 0xE000ED30 is not set to indicate that it was originated by a BKPT instruction This only. occurs if an interrupt other than the debug monitor is already being processed just before. the BKPT is executed,ES0348 Rev 9 7 35, Arm 32 bit Cortex M3 limitations STM32F10xx4 STM32F10xx6. Workaround, If the DFSR register does not have any bit set when the debug monitor is entered this.
means that we must be in this corner case and so that a BKPT instruction was executed. in debug monitor mode, 1 1 4 Cortex M3 may freeze for SLEEPONEXIT single instruction ISR. Description, If the Cortex M3 SLEEPONEXIT functionality is used and the concerned interrupt service. routine ISR contains only a single instruction the core becomes frozen This freezing may. occur if only one interrupt is active and it is preempted by an interrupt whose handler only. contains a single instruction, However any new interrupt that causes a preemption would cause the core to become. unfrozen and behave correctly again,Workaround, This scenario does not happen in real application systems since all enabled ISRs should at. least contain one instruction Therefore if an empty ISR is used then insert an NOP or any. other instruction before the exit instruction BX or BLX. 1 1 5 Interrupted loads to SP can cause erroneous behavior. Description, If an interrupt occurs during the data phase of a single word load to the stack pointer.
SP R13 erroneous behavior can occur In all cases returning from the interrupt results in. the load instruction being executed an additional time For all instructions performing an. update to the base register the base register is erroneously updated on each execution. resulting in the stack pointer being loaded from an incorrect memory location. The affected instructions are,1 LDR SP Rn imm,2 LDR SP Rn imm. 3 LDR SP Rn imm,4 LDR SP Rn,5 LDR SP Rn Rm,Workaround. As of today there is no compiler generating these particular instructions This limitation can. only occur with hand written assembly code, Both issues may be worked around by replacing the direct load to the stack pointer with an. intermediate load to a general purpose register followed by a move to the stack pointer. Example the following instruction LDR SP R0 can be replaced by. 8 35 ES0348 Rev 9, STM32F10xx4 STM32F10xx6 Arm 32 bit Cortex M3 limitations. 1 1 6 SVC and BusFault MemManage may occur out of order. Description, If an SVC exception is generated by executing the SVC instruction while the following.
instruction fetch is faulted then the MemManage or BusFault handler may be entered even. though the faulted instruction which followed the SVC should not have been executed. Workaround, A workaround is only required if the SVC handler does not return to the return address that. has been stacked for the SVC exception and the instruction access after the SVC will fault. If this is the case then padding can be inserted between the SVC and the faulting area of. code for example by inserting NOP instructions,ES0348 Rev 9 9 35. STM32F101x4 6 STM32F102x4 6 and STM32F103x4 6 silicon limitations STM32F10xx4. 2 STM32F101x4 6 STM32F102x4 6 and STM32F103x4 6,silicon limitations. Table 4 gives quick references to all documented limitations. Table 4 Summary of silicon limitations,Links to silicon limitations. Section 2 1 Voltage glitch on ADC input 0, Section 2 2 Flash memory read after WFI WFE instruction.
Section 2 3 Debug registers cannot be read by user software. Section 2 4 Debugging Stop mode and system tick timer. Section 2 5 Debugging Stop mode with WFE entry, Section 2 6 Wakeup sequence from Standby mode when using more than one wakeup source. Section 2 7 LSE start up in harsh environments,Section 2 8 RDP protection. Section 2 9 1 USART1 RTS and CAN TX, Section 2 9 2 SPI1 in slave mode and USART2 in synchronous mode. Section 2 9 3 SPI1 in master mode and USART2 in synchronous mode. Section 2 9 4 I2C with SPI remapped and used in master mode. Section 2 9 Alternate,Section 2 9 5 I2C1 and TIM3 CH2 remapped. Section 2 9 3 SPI1 in master mode and USART2 in synchronous mode. Section 2 9 4 I2C with SPI remapped and used in master mode. Section 2 9 5 I2C1 and TIM3 CH2 remapped,Section 2 9 6 USARTx TX pin usage.
Section 2 10 PVD and USB wakeup events, Section 2 11 Boundary scan TAP wrong pattern sent out after the capture IR state. Section 2 12 Flash memory BSY bit delay versus STRT bit setting. Section 2 13 1 Some software events must be managed before the current. byte is being transferred,Section 2 13 2 Wrong data read into data register. Section 2 13 3 SMBus standard not fully supported, Section 2 13 4 Wrong behavior of I2C peripheral in master mode after a. Section 2 13 I2C misplaced Stop,peripheral, Section 2 13 5 Mismatch on the Setup time for a repeated Start condition. timing parameter, Section 2 13 6 Data valid time tVD DAT violated without the OVR flag being.
Section 2 13 7 I2C analog filter may provide wrong value locking BUSY. flag and preventing master mode entry,10 35 ES0348 Rev 9. STM32F10xx4 STM32F10xx6 STM32F101x4 6 STM32F102x4 6 and STM32F103x4 6 silicon limita. Table 4 Summary of silicon limitations continued,Links to silicon limitations. Section 2 14 1 CRC still sensitive to communication clock when SPI is in. slave mode even with NSS high,Section 2 14 SPI, peripheral Section 2 14 2 SPI CRC may be corrupted when a peripheral connected to. the same DMA channel of the SPI is under DMA transaction close to the end. of transfer or end of transfer 1, Section 2 15 1 Parity Error flag PE is set again after having been cleared. by software, Section 2 15 2 Idle frame is not detected if receiver clock speed is deviated.
STM32F10xx4 6 reference manual for details on how to find the revision code Order code Revision code 2 marked on device 2 Refer to Appendix A for details on how to identify the Revision code on the different packages STM32F101xxxxA 3 3 All MCUs with 16 Kbytes of Flash memory are concerned they all have the letter A in their commercial code Among devices with 32 Kbytes of Flash

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