Recommended Design Rules and Strategies for BGA Devices

Recommended Design Rules And Strategies For Bga Devices-Free PDF

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Revision History, The following table shows the revision history for this document. Date Version Revision,03 01 2016 1 0 Initial Xilinx release. BGA Device Design Rules www xilinx com Send Feedback. UG1099 v1 0 March 1 2016,Table of Contents,Revision History 2. Chapter 1 General BGA and PCB Layout Overview,Introduction 5. Pitch Size 6,BGA Landing Pads 7,Chapter 2 Layer Count Estimation and Optimization.
Layer Count Estimation 8,Layer Count Optimization 10. Maximum Board Thickness 12, Chapter 3 Recommended Layout Dimensions within BGA Area for 1 0 mm Pitch. BGA Ball Pad and Via Dimensions 13,Trace Widths Dimensions inside the BGA Area 17. Trace Routing Between Vias 20, Sample Breakouts using Standard and Advanced Processes 21. Chapter 4 Recommended Layout Dimensions within BGA Area for 0 8 mm Pitch. BGA Ball Pad and Via Dimensions 30,Trace Widths Dimensions inside BGA Area 32.
Trace Routing Between Vias 34, Sample Breakouts using Standard and Advanced PCB Processes 35. Chapter 5 Recommended Layout Dimensions within BGA Area for 0 5 mm Pitch. BGA Ball Pad and Via Dimensions 42,Trace Widths Dimensions inside BGA Area 44. Trace Routing Between Vias 45,Sample Breakout Using Advanced Process 45. BGA Device Design Rules www xilinx com Send Feedback. UG1099 v1 0 March 1 2016,Chapter 6 Power Delivery to the FPGA. Appendix A Additional Resources and Legal Notices,Xilinx Resources 52.
Solution Centers 52,References 52,Please Read Important Legal Notices 52. BGA Device Design Rules www xilinx com Send Feedback. UG1099 v1 0 March 1 2016,General BGA and PCB Layout Overview. Introduction, Xilinx UltraScale architecture 7 series and 6 series devices come in a variety of. packages that are designed for maximum performance and maximum flexibility Three pitch. sizes are available for these packages 1 0 mm 0 8 mm and 0 5 mm In general as the pitch. size decreases the challenges for PCB routing increase as there is less room to route traces. and vias between package balls This guide illustrates various methods for successful design. regardless of pitch size, Note Throughout this guide various specifications and estimates are given regarding PCB pricing. costs and technology As PCB manufacturing technology is constantly advancing it is highly advised. to consult with your PCB manufacturer to fully understand their capabilities regarding the. information presented here, BGA Device Design Rules www xilinx com Send Feedback.
UG1099 v1 0 March 1 2016,Chapter 1 General BGA and PCB Layout Overview. Pitch Size, Pitch size is defined as the distance between consecutive balls on a BGA package measured. from center to center as shown in Figure 1 1,X Ref Target Figure 1 1. Figure 1 1 Definition of Pitch Size, BGA Device Design Rules www xilinx com Send Feedback. UG1099 v1 0 March 1 2016,Chapter 1 General BGA and PCB Layout Overview.
BGA Landing Pads, Xilinx recommends using Non Solder Mask Defined NSMD copper BGA landing pads for. optimum board design NSMD pads are pads that are not covered by any solder mask as. opposed to Solder Mask Defined SMD pads in which a small amount of solder mask covers. the pad landing Figure 1 2 illustrates the difference between NSMD and SMD pads. X Ref Target Figure 1 2,RSSHU 3DG 6ROGHU 0DVN RSSHU 3DG. 160 3DG 60 3DG,Figure 1 2 NSMD and SMD Pads, BGA Device Design Rules www xilinx com Send Feedback. UG1099 v1 0 March 1 2016,Layer Count Estimation and Optimization. Layer Count Estimation, A quick way to estimate the number of routing layers required to fully break out signal pins.
from the FPGA would be to use Equation 2 1,Layers Equation 2 1. Routing Channels Routes Per Channel, For Xilinx FPGAs the amount of signals is approximately 60 of the number of BGA balls. The other 40 are power and ground signals that are most often routed directly down to. planes by vias This is assuming full I O utilization If fewer I Os are used then the number. of signals to route goes down accordingly, Routing channels are the number of available routing paths out of the BGA area the. number of BGA pins on one side minus one times four sides Figure 2 1 shows a 5x5 grid. with sixteen total routing channels four routing channels per side times four sides. BGA Device Design Rules www xilinx com Send Feedback. UG1099 v1 0 March 1 2016,Chapter 2 Layer Count Estimation and Optimization. X Ref Target Figure 2 1, Figure 2 1 Definition of Routing Channel 16 Total Routing Channels Shown.
BGA Device Design Rules www xilinx com Send Feedback. UG1099 v1 0 March 1 2016,Chapter 2 Layer Count Estimation and Optimization. Routes per channel is either one or two depending on whether one or two signals are. routed between BGA pads The approximate number of layers required to fully route out a. Xilinx FPGA are shown in Table 2 1, Table 2 1 Approximate Signal Layers per of Package Pins. Signal Layer Counts,Ball Pitch All Available IOs Routed. BGA Pins Routes Per Channel,196 0 5 N A 2,225 0 8 2 3. 236 0 5 N A 3,256 1 0 2 3,324 0 8 2 3,400 0 8 2 3,484 0 8 3 4.
484 1 0 2 4,625 0 8 3 4,676 1 0 3 5,784 0 8 4 5,784 1 0 3 5. 900 1 0 3 5,1156 1 0 3 6,1517 1 0 4 7,1760 1 0 4 8. 1924 1 0 4 8,2104 1 0 4 8,2377 1 0 5 9,2577 1 0 5 9. 2892 1 0 5 10,Layer Count Optimization, UltraScale architecture 7 series and 6 series packages have full matrices of solder balls The. number of layers required for effective routing of these packages is dictated by a variety of. factors including,BGA Size amount of pins,Pad size pad pitch and trace width.
Fixed pinouts, BGA Device Design Rules www xilinx com Send Feedback. UG1099 v1 0 March 1 2016,Chapter 2 Layer Count Estimation and Optimization. Fabrication technologies, The amount of pins in a BGA indicates the amount of signals to route Because of physical. space constraints the amount of signals required to route is proportional to the amount of. signal layers required,Pad Size Pad Pitch and Trace Width. The pad size and pitch determines the available space between adjacent balls for signal. escape Based on the chosen trace width one or two signals can be routed between. adjacent pads If one signal escapes between adjacent pads then one signal row can be. routed on a single metal layer The exception to this is the outermost row which allows two. routes per layer, To facilitate routing in the ball grid area necking down the trace width in the critical space.
between the BGA pads vias the breakout area is allowable This then allows for two signal. rows to be routed on a single metal layer or three if routing the outermost row. The traces can then be widened after they escape the breakout area Changes in width over. very short distances can cause small impedance changes Validate these issues with the. board vendor and signal integrity engineers responsible for the design. Fixed Pinouts, Xilinx FPGA pinouts are designed with maximum flexibility in mind However certain FPGA. signals such as JTAG transceiver inputs and outputs and Interlaken signals among others. have fixed locations which means routing of these signals is limited compared to other. signals that can be swapped as needed Fixed locations lead to layout trade offs that can. have an impact on the number of required signal layers. Fabrication Technologies, Several advanced fabrication technologies can be used to reduce the amount of layers. required to route a design although each of these technologies increase fabrications costs. of the board, Blind Vias 20 to 40 fabrication cost As opposed to a through hole via a blind. via does not travel from the top layer to the bottom layer A blind via travels either from the. top or bottom layer to an inner signal layer freeing up room above or below for other. Buried Vias 25 to 60 fabrication cost A buried via is located entirely inside the. printed circuit board and does not touch the top or bottom layers. BGA Device Design Rules www xilinx com Send Feedback. UG1099 v1 0 March 1 2016,Chapter 2 Layer Count Estimation and Optimization. Micro Vias 30 fabrication cost A micro via is either a blind or buried via only much. smaller Micro Vias are most often used in small high density applications such as cell. Back drilled Vias 10 fabrication cost A back drilled via is a through hole via that. has a portion of its length drilled out such that it is no longer conductive This improves. signal integrity as it removes an unneeded stub from the route. Via In Pad 30 fabrication cost A via in pad is a via drilled directly beneath a pad. This removes the need for a separate metal trace to be drawn to drop down a via This can. result in improved signal integrity because of lower inductance but the trade off is a much. higher board fabrication cost, Extra Layers 20 fabrication cost per every two layers It might be such that the.
cost to add two or more extra signal layers is lower than the cost to add an advanced. technology so adding layers is not always to be considered a negative alternative. Maximum Board Thickness, The maximum board thickness is a function of the minimum drill diameter and aspect ratio. both of which are provided by the PCB manufacturer A typical aspect ratio of 10 1 indicates. that the board can be no thicker than ten times the drill diameter A drill diameter of. 13 mils for example would lead to a maximum board thickness of 130 mils With the. exception of the CP package Xilinx recommends finished drill diameters to be 10 mils. which translates to an actual drill diameter of about 13 mils plating typically reduces the. diameter by about 3 mils A 13 mil drill would lead to a maximum board thickness of. 130 mils assuming a 10 1 aspect ratio For the CP package the finished drill diameter of. 6 mils approximates a drill diameter of 9 mils or a maximum board thickness of 90 mils. If a higher board thickness than the drill diameter and aspect ratio can support is required. the use of buried or blind vias can be used but at a higher manufacturing cost. BGA Device Design Rules www xilinx com Send Feedback. UG1099 v1 0 March 1 2016,Recommended Layout Dimensions within. BGA Area for 1 0 mm Pitch Devices,BGA Ball Pad and Via Dimensions. The amount of space available for routing under the FPGA is dependent on the area. between the balls in the BGA area for top and bottom layers as well as the area between. vias for inner layers The typical dimensions of FPGA ball pads and vias for 1 0 mm pitch. devices are described in Figure 3 1 through Figure 3 4. X Ref Target Figure 3 1,6ROGHU 0DVN,EHWZHHQ 9LD LQLVKHG. 9LD DQG ROH LDPHWHU,9LD 3ODWLQJ, Figure 3 1 Ball and Via Dimensions for 1 0mm Pitch FB and FT Devices mils.
BGA Device Design Rules www xilinx com Send Feedback. UG1099 v1 0 March 1 2016, Chapter 3 Recommended Layout Dimensions within BGA Area for 1 0 mm Pitch Devices. X Ref Target Figure 3 2,6ROGHU 0DVN,9LD LQLVKHG,9LD 3ODWLQJ. Figure 3 2 Ball and Via Dimensions for 1 0mm Pitch FB and FT Devices mm. BGA Device Design Rules www xilinx com Send Feedback. UG1099 v1 0 March 1 2016, Chapter 3 Recommended Layout Dimensions within BGA Area for 1 0 mm Pitch Devices. X Ref Target Figure 3 3,6ROGHU 0DVN,EHWZHHQ 9LD LQLVKHG. 9LD DQG ROH LDPHWHU,9LD 3ODWLQJ, Figure 3 3 Ball and Via Dimensions for 1 0mm Pitch FF FG FH FL RB and RF Devices mils.
BGA Device Design Rules www xilinx com Send Feedback. BGA Device Design Rules www xilinx com 7 UG1099 v1 0 March 1 2016 Chapter 1 General BGA and PCB Layout Overview BGA Landing Pads Xilinx recommends using Non Solder Mask Defined NSMD copper BGA landing pads for

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