New No The DEC PDP 11 Gordon Bell

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650 Part 3 I,Computer Classes Section 3 I,Minicomputers. The machine is described using the PMS and ISP notation of machines Although the selling price was constrained to lie in the. Bell and Newell 1971 at difiFerent levels The, following descrip 5 000 to 10 000 range it was realized that the decreasing cost of. tive sections correspond to the levels external design constraints logic would allow a more complex organization than earlier DEC. level the PMS level, the way components are interconnected computers A design which could take advantage of medium and. and allow information to flow the program level or ISP Instruc eventually large scale integration was an important consideration. tion Set Processor, the abstractmachine which interprets First it could make the computer perform well and second it. programs and finally the logical design level We omit a would extend the computer family s life For these reasons a. discussion of the circuit level, the PDP 11 being constructed general registers organization was chosen.
from TTL integrated circuits, Interrupt Response Since the PDP 11 will be used for real time. control applications important that devices can communicate. Design Constraints with one another quickly i e the response time of a request. should be short A multiple priority level nested interrupt. The principal design objective is yet to be tested namely do. mechanism was selected additional priority levels are provided. users like the machine This will be tested both in the market by the physical position of a device on the Unibus Software. place and by the features that are emulated in newer machines it polling is unnecessary because each device interrupt corresponds. will indirectlybe tested by the life span of the PDP 11 and any to a unique address. ofiFspring,Word Length The of course the main objective. total system including software is,The most word length defined by IBM was. critical constraint of the design Two,techniques were used to aid programmability. chosen to be a multiple of 8 bits The memory word length for the first benchmarks gave a continuous indication as to how well the. Model 20 is 16 bits although there are 32 and 48 bit instructions machine interpreted programs second systems programmers. and 8 and 16 bit data Other members of the family might have continually evaluated the design Their evaluation considered. up to 80 bit instructions with 8 16 32 and 48 bit data The what code the compiler would produce how would the loader. internal and preferred external character set was chosen to be work ease of program relocability the use of a debugging. 8 bit ASCII program how the compiler assembler and editor would be. coded in effect other benchmarks how real time monitors. Range and Performance would be written to use the various facilities and present a clean. interface to the users finally the ease of coding a program. Performance and ftinction range extendability were the main. design constraints in fact they were the main reasons to build a. new computer DEC already has 4 computer families that span a Modularity. range but are incompatible In addition to the range the initial Structural flexibility sometimes called modularity for a particular. machine was constrained to fall within the small computer model was desired A flexible and straightforward method for. product line which means to have about the same performance as interconnecting components had to be used because of varying. a PDP 8 The initial machine outperforms the PDP 5 LINC and user needs among user classes and over time Users should have. PDP 4 based families Performance of course is both a function the ability to configure an optimum system based on cost. of the instruction set and the technology Here we re fundamen performance and reliability both by interconnection and when. tally only concerned with the instruction set performance because necessary new components Since users build. constructing, faster hardware will always increase performance for.
any family special hardware a computer should be easily interfaced As a. Unlike the earlier DEC families the PDP 11 had be designed. to by product of modularity computer components can be produced. so that new models with significantly more performance can be and stocked rather than tailor made on order The physical. added to the family structure is almost identical to the PMS structure discussed in the. A rather obvious goal is maximum performance for a given following section thus reasonably large building blocks are. model Designs were programmed using benchmarks and the available to the user. results compared with both DEC and potentially,competitive. Microprogramming, PDP 4 7 9 15 family PDP 5 8 8 S 8 1 8 L family LINC PDP A note on microprogramming is in order because of current. 8 LINC PDP 12 fkmily and PDP 6 10 family The initial PDP 1 did not interest in the firmware concept We. believe microprogram, achieve family status ming as we understand it Wilkes 1951 can be a worthwhile. Chapter 38 A New Architecture for Mini Computers The DEC PDP 11 651. technique as applies to processor design For example micro. programming can probably be used in larger computers when proc a or. floating point data operators are needed The IBM System 360 has. made use of the technique for defining processors that interpret. both the System 360 instruction set and earlier family instruction prisary k Unlbui. sets e g 1401 1620 7090 In the PDP 11 the basic instruction cooponenta. set is quite straightforward and does not necessitate micropro. grammed The processor memory connection is,interpretation concrol. asynchronous and therefore memory of any speed can be connect. coodary taralnals, instruction set encourages the user to write reentrant.
ory g Tela, programs thus read only memory can be used as part of primary parlphcry. memory to the permanency and performance normally, attributed to microprogramming In fact the Model 10 computer. which will not be further discussed has a 1024 word read only. memory and a 128 word read write memory,Convtfnclonal block dlagraa. Vnderstandability, Understandability was perhaps the most fundamental constraint. or goal although it is now somewhat less important to have a. machine that can be quickly understood by a novice computer. user than it was a few years ago DEC s early success has been. predicated on selling to an intelligent but inexperienced user Pc. Understandability though hard to measure is an important goal. because all potential users must understand the computer A I. straightforward design should simplify the systems programming parlphcry. task in the case of a compiler it should make translation. particularly code generation easier,FMS dlacrav,PDP 11 Structure at the PMS Level.
Introduction, PDP 11 has the same organizational structure as nearly all present. it X aaaa X ia aa allaa abbrcvlatloa, day computers Fig primitive PMS components are the. 1 The for caapoMBC la aaparatad by, primary memory Mp which holds the programs while the central a la aaalgsad ttM. Maolas of b,dallalta autualljr aKclualva altar, processor Pc interprets them io controls Kio which manage Mitlvaa. data transfers between terminals T or secondary memories Ms Coaponcats Proc or p a t of prlaltlva c. H Bory H Swlcch s their abbravlaciona, to primary memory Mp the components outside the computer at Cootrol lC T r lMl T.
Data operatloo DlUok Ll, periphery X either humans H or some external process e g Hu a H. another computer the processor console T console by which X a v y a aetrlbuta a valua v palra. Attrlbuta aay ba oalttad If it, humans communicate with the computer and observe its behavior can b Ufarrad fro dlMnaloaa. and affect changes in its state and a switch S with its control K tadaa auabar f. attrlbutt tlvU coapoocnt nuabar, which allows all the other components to communicate with one aa a attrlbuCa giving eo onaat na. another In the case of PDP 11 the central switch,Icccllaacou abbrevlatloas. logical Mp prlaary waory Ha iccondarr aaorylPe caatral. Klo to control Plo io proccsaor procaaaorl, structure implemented using a bus or chained switch S called.
b blt v ord l lBforMtioa,ac aacond char charactar, the Unibus as shown in Fig 2 Each physical component has a InforMtlon carrying link. bl dlractlonal,latl dlraccioaal InforMtloi,carrying Itnka. A descriptive block diagram level Bell and Newell 1971 to describe dallalta altamaClvaa. the relationship of the computer components processors memories. switches controls links terminals and data operators Conventional block diagram and PMS. Fig 1 diagram of PDP 11, 652 Part 3 Computer Classes Section 3 I Minicomputers. The device signals for attention using the interrupt dia. coaputer h, periphery logue and the central processor responds by managing the. data transmission in a fashion similar to transmitting. initialization information, Np Fc Ki 5 Some device controls for T or Ms transfer data directly.
S S Unlbus switching,I 1 n structure, to from primary memory without central processor inter. vention In this mode the device behaves similar to a. processor a memory address is specified and the data is. transmitted between the device and primary memory,Unlbus control packaged with Pc. 6 The transfer of data between two controls e g a secon. PDP 1 1 physical structure PMS dary memory disk and say a terminal T display is not. Fig 2 diagram,precluded provided the two use compatible message. switch for placing messages on the bus or taking messages off the. bus The central control decides the next component to use the As we show more detail in the structure there are of course. bus message call The S Unibus differs from most switches. for a more messages and more simultaneous activity The above does. because any component can communicate with any other compo not describe the shared control and its associated switching which. magnetic tape and magnetic disk secondary memory,typical of a. The types of messages in the PDP 11 are along the lines of the systems A control for a DECtape memory Fig 3 has an. hierarchical structure common to present day computers The S DECtape bus for transmitting data between a single tape unit. single bus makes conventional and other structures possible and the DECtape transport The existence of this kind of structure. The message processes in the structure which utilize S Unibus is based on the relatively high cost of the control relative to the. are cost of the tape and the value of being able to run concurrently. with other tapes There is also a dialogue at the periphery. 1 The central processor Pc requests that data be read or between X T and X Ms which does not use the Unibus For. written from or to primary memory Mp for instructions example the removal of a magnetic tape reel from a tape unit or a. and data The processor calls a particular memory module human user H striking a typewriter key are typical dialogues. by concurrently specifying the module s address and the All of these dialogues lead to the hierarchy of present comput. address within the modules Depending on whether the ers Fig we. can see the paths by which the,In this hierarchy, processor requests reading or writing data is transmitted above messages are passed Pc Mp Pc K K Pc Kio T and.
either from the memory to the processor or vice versa. Kio Ms and Kio Mp and at the periphery T X and T Ms and. 2 The central processor Pc controls the initialization of T console H. secondary memory Ms and terminal T activity The, processor sets status bits in the control associated with a Model 20 Implementation. particular Ms or T and the device proceeds with the. specified action e g reading a card or punching a Figure 5 shows the detailed structure of a uni processor Model 20. character into paper tape Since some devices transfer data PDP 11 with its various components options In Fig 5 the. vectors directly to primary memory the vector control Unibus characteristics are suppressed The detailed properties of. information i e the memory location and length is given the switch are described in the logical design section. as initialization information, 3 Controls request the processor s attention in the form of. Ms 0 7 DECtape, interrupts An interrupt request to the processor has the. effect of changing the state of the processor thus the. processor begins executing a program associated with the. interrupting process Note the interrupt process is only a SpDECtape bus. Iconcurrency i, signaling method and when the processor interruption. occurs the interruptee specifies a unique address value to. the processor The address is a starting address for a Kio DECtape. The central processor can control the transmission of data. between a control for T or Ms and either the processor or. a primary memory for program controlled data transfers Fig 3 DECtape control switching PMS diagram. Chapter 38 I A New Architecture for Mini Computers The DEC PDP 11 653. Fig 4 Conventional hierarchy computer structure,Extensions to Increase Performance.
The reader should note Fig 5 that the important limitations of. the bus are a concurrency of one namely only one dialogue can. occur at a given time and a maximum transfer rate of one 16 bit. word per 75 jLsec giving a transfer rate of 21 3 megabits second. While the bus is not a limit for a uni processor structure it is a. InterruptResponse SincethePDP 11willbeusedforrealtime controlapplications itis important that devicescan communicate with one anotherquickly i e theresponsetimeof a request

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