M12L64164A 2C 1 ESMT

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ESMT M12L64164A 2C,FUNCTIONAL BLOCK DIAGRAM,Generator Bank D. Address Row,Row Decoder,Mode Bank A,Register Refresh. Sense Amplifier,Command Decoder,CS Address Column Decoder. Control Logic,Input Output,Latch Circuit,Data Control Circuit DQ. PIN FUNCTION DESCRIPTION,PIN NAME INPUT FUNCTION, CLK System Clock Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all. CS Chip Select inputs except CLK CKE and L U DQM, Masks system clock to freeze operation from the next clock cycle. CKE Clock Enable CKE should be enabled at least one cycle prior new command. Disable input buffers for power down in standby, A0 A11 Address Row column address are multiplexed on the same pins. Row address RA0 RA11 column address CA0 CA7, BA1 BA0 Bank Select Address Selects bank to be activated during row address latch time. Selects bank for read write during column address latch time. Latches row addresses on the positive going edge of the CLK with. RAS Row Address Strobe RAS low,Enables row access precharge. Latches column address on the positive going edge of the CLK with. CAS Column Address Strobe CAS low,Enables column access.
Enables write operation and row precharge,WE Write Enable. Latches data in starting from CAS WE active, Makes data output Hi Z tSHZ after the clock and masks the output. L U DQM Data Input Output Mask,Blocks data input when L U DQM active. DQ0 DQ15 Data Input Output Data inputs outputs are multiplexed on the same pins. VDD VSS Power Supply Ground Power and ground for the input buffers and the core logic. Isolated power supply and ground for the output buffers to provide. VDDQ VSSQ Data Output Power Ground improved noise immunity. NC No Connection This pin is recommended to be left No Connection on the device. Elite Semiconductor Memory Technology Inc Publication Date Aug 2017. Revision 1 1 2 45,ESMT M12L64164A 2C,ABSOLUTE MAXIMUM RATINGS. PARAMETER SYMBOL VALUE UNIT, Voltage on any pin relative to VSS VIN VOUT 1 0 4 0 V.
Voltage on VDD supply relative to VSS VDD VDDQ 1 0 4 0 V. Operating ambient temperature TA 0 70 C,Storage temperature TSTG 55 150 C. Power dissipation PD 1 W,Short circuit current IOS 50 mA. Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITION, Recommended operating conditions Voltage referenced to VSS 0V. PARAMETER SYMBOL MIN TYP MAX UNIT NOTE,Supply voltage VDD VDDQ 3 0 3 3 3 6 V. Input logic high voltage VIH 2 0 3 0 VDD 0 3 V 1,Input logic low voltage VIL 0 3 0 0 8 V 2.
Output logic high voltage VOH 2 4 V IOH 2mA,Output logic low voltage VOL 0 4 V IOL 2mA. Input leakage current IIL 5 5 A 3,Output leakage current IOL 5 5 A 4. Note 1 VIH max 4 0V AC for pulse width 1 10 CLK pulse width. 2 VIL min 1 0AC for pulse width 1 10 CLK pulse width. 3 Any input 0V VIN VDD all other pins are not under test 0V. 4 Dout is disabled 0V VOUT VDD,CAPACITANCE VDD 3 3V TA 25 C f 1MHz. PARAMETER SYMBOL MIN MAX UNIT,Input capacitance A0 A11 BA0 BA1 CIN1 2 5 4 5 pF. Input capacitance,CLK CKE CS RAS CAS WE CIN2 2 4 pF.
Data input output capacitance DQ0 DQ15 COUT 2 5 4 5 pF. Elite Semiconductor Memory Technology Inc Publication Date Aug 2017. Revision 1 1 3 45,ESMT M12L64164A 2C,DC CHARACTERISTICS. Recommended operating condition unless otherwise noted. PARAMETER SYMBOL TEST CONDITION UNIT NOTE, Operating Current Burst Length 1 tRC tRC min IOL 0 mA. ICC1 60 50 40 mA 1 2,One Bank Active tCC tCC min,ICC2P CKE VIL max tCC tCC min 2. Precharge Standby Current mA,in power down mode ICC2PS CKE CLK VIL max tCC 2. ICC2N CKE VIH min CS VIH min tCC tCC min 20,Input signals are changed one time during 2CLK.
Precharge Standby Current mA, in non power down mode CKE VIH min CLK VIL max tCC. input signals are stable, Active Standby Current ICC3P CKE VIL max tCC tCC min 8. in power down mode ICC3PS CKE CLK VIL max tCC 8,CKE VIH min CS VIH min tCC 15ns. Active Standby Current ICC3N Input signals are changed one time during 2clks 30 mA. in non power down mode All other pins VDD 0 2V or 0 2V. One Bank Active,ICC3NS CKE VIH min CLK VIL max tCC. input signals are stable, Operating Current IOL 0 mA Page Burst All Bank active.
ICC4 80 70 60 mA 1 2,Burst Mode Burst Length 4 CAS Latency 3. Refresh Current ICC5 tRFC tRFC min tCC tCC min 65 55 45 mA. Self Refresh Current ICC6 CKE 0 2V 2 mA,Note 1 Measured with outputs open. 2 Input signals are changed one time during 2 CLKS. Elite Semiconductor Memory Technology Inc Publication Date Aug 2017. Revision 1 1 4 45,ESMT M12L64164A 2C,AC OPERATING TEST CONDITIONS VDD 3 3V 0 3V. PARAMETER VALUE UNIT,Input levels Vih Vil 2 4 0 4 V. Input timing measurement reference level 1 4 V,Input rise and fall time tr tf 1 1 ns.
Output timing measurement reference level 1 4 V,Output load condition See Fig 2. 3 3V Vtt 1 4V,VOH DC 2 4V IOH 2 mA,Output Output Z0 50. VOL DC 0 4V IOL 2 mA, Fig 1 DC Output Load Circuit Fig 2 AC Output Load Circuit. OPERATING AC PARAMETER,AC operating conditions unless otherwise noted. PARAMETER SYMBOL UNIT NOTE, Row active to row active delay tRRD min 10 12 14 ns 1.
RAS to CAS delay tRCD min 15 18 21 ns 1,Row precharge time tRP min 15 18 21 ns 1. tRAS min 38 40 42 ns 1,Row active time,tRAS max 100 us. Operating tRC min 53 58 63 ns 1, Row cycle time Auto refresh tRFC min 55 60 70 ns 1 5. Last data in to col address delay tCDL min 1 CLK 2. Last data in to row precharge tRDL min 3 CLK 2,Last data in to burst stop tBDL min 1 CLK 2. Col address to col address delay tCCD min 1 CLK 3,Refresh period 4 096 rows tREF max 64 ms 6.
Number of valid CAS latency 3 2,Output data CAS latency 2 1. 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then. rounding off to the next higher integer,2 Minimum delay is required to complete with. 3 All parts allow every cycle column address change. 4 In case of row precharge interrupt auto precharge and read burst stop. 5 A new command may be given tRFC after self refresh exit. 6 A maximum of eight consecutive AUTO REFRESH commands with tRFC min can be posted to any given SDRAM and. the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is. Elite Semiconductor Memory Technology Inc Publication Date Aug 2017. Revision 1 1 5 45,ESMT M12L64164A 2C, AC CHARACTERISTICS AC operating condition unless otherwise noted. PARAMATER SYMBOL UNIT NOTE,MIN MAX MIN MAX MIN MAX. CAS latency 3 5 6 7,CLK cycle time tCC 1000 1000 1000 ns 1.
CAS latency 2 7 5 9 8 9 8,CLK to valid CAS latency 3 5 5 5 6. output delay tSAC ns 1 2,CAS latency 2 6 6 6,Output data CAS latency 3 2 2 5 2 5. hold time tOH ns 2,CAS latency 2 2 2 5 2 5,CLK high pulse width tCH 2 2 5 2 5 ns 3. CLK low pulse width tCL 2 2 5 2 5 ns 3,Input setup time tSS 1 5 1 5 1 5 ns 3. Input hold time tSH 0 8 0 8 0 8 ns 3,CLK to output in Low Z tSLZ 0 0 0 ns 2.
CLK to output CAS latency 3 4 5 5 5 6,in Hi Z tSHZ ns. CAS latency 2 6 6 6, Note 1 Parameters depend on programmed CAS latency. 2 If clock rising time is longer than 1ns tr 2 0 5 ns should be considered. 3 Assumed input rise and fall time tr tf 1ns, If tr tf is longer than 1ns transient time compensation should be considered. i e tr tf 2 1 ns should be added to the parameter, Elite Semiconductor Memory Technology Inc Publication Date Aug 2017. Revision 1 1 6 45,ESMT M12L64164A 2C,SIMPLIFIED TRUTH TABLE.
COMMAND CKEn 1 CKEn CS RAS CAS WE DQM A10 AP Note, Register Mode Register set H X L L L L X OP CODE 1 2. Auto Refresh H 3,H L L L H X X,Refresh Self,L H H H X 3. Refresh Exit L H X,H X X X X 3,Bank Active Row Addr H X L L H H X V Row Address. Read Auto Precharge Disable L Column 4,H X L H L H X V Address. Column Address Auto Precharge Enable H A0 A7 4 5,Write Auto Precharge Disable L Column 4.
H X L H L L X V Address,Column Address Auto Precharge Enable H A0 A7 4 5. Burst Stop H X L H H L X X 6,Bank Selection V L,Precharge H X L L H L X X. All Banks X H,Clock Suspend or Entry H L X,Active Power Down Mode X. Exit L H X X X X X,Entry H L X,Precharge Power Down Mode. Exit L H X,DQM H X V X 7,No Operating Command H X X X.
V Valid X Don t Care H Logic High L Logic Low,Note 1 OP Code Operating Code. A0 A11 BA0 BA1 Program keys MRS, 2 MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3 Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge of command is meant by Auto. Auto self refresh can be issued only at all banks idle state. 4 BA0 BA1 Bank select addresses, If both BA0 and BA1 are Low at read write row active and precharge bank A is selected. If both BA0 is Low and BA1 is High at read write row active and precharge bank B is selected. If both BA0 is High and BA1 is Low at read write row active and precharge bank C is selected. If both BA0 and BA1 are High at read write row active and precharge bank D is selected. If A10 AP is High at row precharge BA0 and BA1 is ignored and all banks are selected. 5 During burst read or write with auto precharge new read write command can not be issued. Another bank read write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6 Burst stop command is valid at every burst length. 7 DQM sampled at positive going edge of a CLK and masks the data in at the very CLK write DQM latency is 0 but. makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2. Elite Semiconductor Memory Technology Inc Publication Date Aug 2017. Revision 1 1 7 45,ESMT M12L64164A 2C,MODE REGISTER FIELD TABLE TO PROGRAM MODES. Register Programmed with MRS, Address BA0 BA1 A11 A10 AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0.
Function RFU RFU W B L TM CAS Latency BT Burst Length. Test Mode CAS Latency Burst Type Burst Length, A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT 0 BT 1. 0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1. 0 1 Reserved 0 0 1 Reserved 1 Interleave 0 0 1 2 2. 1 0 Reserved 0 1 0 2 0 1 0 4 4,1 1 Reserved 0 1 1 3 0 1 1 8 8. Write Burst Length 1 0 0 Reserved 1 0 0 Reserved Reserved. A9 Length 1 0 1 Reserved 1 0 1 Reserved Reserved,0 Burst 1 1 0 Reserved 1 1 0 Reserved Reserved. 1 Single Bit 1 1 1 Reserved 1 1 1 Full Page Reserved. Full Page Length 256, Note 1 RFU Reserved for future use should stay 0 during MRS cycle. 2 If A9 is high during MRS cycle Burst Read Single Bit Write function will be enabled. 3 The full column burst 256 bit is available only at sequential mode of burst type. Elite Semiconductor Memory Technology Inc Publication Date Aug 2017. Revision 1 1 8 45,ESMT M12L64164A 2C,BURST SEQUENCE BURST LENGTH 4.
Initial Address,Sequential Interleave,0 0 0 1 2 3 0 1 2 3. 0 1 1 2 3 0 1 0 3 2,1 0 2 3 0 1 2 3 0 1,1 1 3 0 1 2 3 2 1 0. BURST SEQUENCE BURST LENGTH 8,Initial Address,Sequential Interleave. 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7,0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6. 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5,0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4.
1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3,1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2. 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1,1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0. Elite Semiconductor Memory Technology Inc Publication Date Aug 2017. Revision 1 1 9 45,ESMT M12L64164A 2C,DEVICE OPERATIONS. CLOCK CLK POWER UP, The clock input is used as the reference for all SDRAM 1 Apply power and start clock Attempt to maintain CKE. operations All operations are synchronized to the positive H DQM H and the other pins are NOP. going edge of the clock The clock transitions must be condition at the inputs. monotonic between VIL and VIH During operation with CKE 2 Maintain stable power stable clock and NOP input. high all inputs are assumed to be in valid state low or high condition for minimum of 200us. for the duration of setup and hold time around positive edge 3 Issue precharge commands for all banks of the. of the clock for proper functionality and Icc specifications devices. 4 Issue 2 or more auto refresh commands, 5 Issue a mode register set command to initialize the.
CLOCK ENABLE CKE mode register,cf Sequence of 4 5 is regardless of the order. The clock enable CKE gates the clock onto SDRAM If. CKE goes low synchronously with clock set up and hold The device is now ready for normal operation. time same as other inputs the internal clock suspended. from the next clock cycle and the state of output and burst. address is frozen as long as the CKE remains low All other MODE REGISTER SET MRS. inputs are ignored from the next clock cycle after CKE goes. low When all banks are in the idle state and CKE goes low The mode register stores the data for controlling the. synchronously with clock the SDRAM enters the power various operating modes of SDRAM It programs the. ESMT M12L64164A 2C Elite Semiconductor Memory Technology Inc Publication Date Aug 2017 Revision 1 1 6 45 AC CHARACTERISTICS AC operating condition unless otherwise noted PARAMATER SYMBOL 5 6 7 UNIT NOTE MIN MAX MIN MAX MIN MAX CLK cycle time CAS latency 3 tCC 5 1000 6 1000 7 1000 ns 1

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