LOGIC DESIGN LABORATORY MANUAL ElectricVLab

Logic Design Laboratory Manual Electricvlab-Free PDF

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Logic Design Laboratory Manual 1,EXPERIMENT 1 LOGIC GATES. AIM To study and verify the truth table of logic gates. LEARNING OBJECTIVE,Identify various ICs and their specification. COMPONENTS REQUIRED,Logic gates IC trainer kit,Connecting patch chords. IC 7400 IC 7408 IC 7432 IC 7406 IC 7402 IC 7404 IC 7486. The basic logic gates are the building blocks of more complex logic circuits These logic. gates perform the basic Boolean functions such as AND OR NAND NOR Inversion. Exclusive OR Exclusive NOR Fig below shows the circuit symbol Boolean function and. truth It is seen from the Fig that each gate has one or two binary inputs A and B and one. binary output C The small circle on the output of the circuit symbols designates the logic. complement The AND OR NAND and NOR gates can be extended to have more than two. inputs A gate can be extended to have multiple inputs if the binary operation it represents is. commutative and associative, These basic logic gates are implemented as small scale integrated circuits SSICs or as part. of more complex medium scale MSI or very large scale VLSI integrated circuits Digital. IC gates are classified not only by their logic operation but also the specific logic circuit. family to which they belong Each logic family has its own basic electronic circuit upon. which more complex digital circuits and functions are developed The following logic. families are the most frequently used,TTL Transistor transistor logic.
ECL Emitter coupled logic,MOS Metal oxide semiconductor. CMOS Complementary metal oxide semiconductor, TTL and ECL are based upon bipolar transistors TTL has a well established popularity. among logic families ECL is used only in systems requiring high speed operation MOS and. CMOS are based on field effect transistors They are widely used in large scale integrated. circuits because of their high component density and relatively low power consumption. CMOS logic consumes far less power than MOS logic There are various commercial. Logic Design Laboratory Manual 2, integrated circuit chips available TTL ICs are usually distinguished by numerical designation. as the 5400 and 7400 series,1 Check the components for their working. 2 Insert the appropriate IC into the IC base, 3 Make connections as shown in the circuit diagram.
4 Provide the input data via the input switches and observe the output on output LEDs. Logic Design Laboratory Manual 3,VIVA QUESTIONS,1 Why NAND NOR gates are called universal gates. 2 Realize the EX OR gates using minimum number of NAND gates. 3 Give the truth table for EX NOR and realize using NAND gates. 4 What are the logic low and High levels of TTL IC s and CMOS IC s. 5 Compare TTL logic family with CMOS family, 6 Which logic family is fastest and which has low power dissipation. EXPERIMENT 2 REALIZATION OF A BOOLEAN FUNCTION, AIM To simplify the given expression and to realize it using Basic gates and. Universal gates,LEARNING OBJECTIVE, To simplify the Boolean expression and to build the logic circuit. Given a Truth table to derive the Boolean expressions and build the logic circuit to. realize it,COMPONENTS REQUIRED, IC 7400 IC 7408 IC 7432 IC 7406 IC 7402 Patch Cords IC Trainer Kit.
Canonical Forms Normal Forms Any Boolean function can be written in disjunctive. normal form sum of min terms or conjunctive normal form product of max terms. A Boolean function can be represented by a Karnaugh map in which each cell corresponds to. a minterm The cells are arranged in such a way that any two immediately adjacent cells. correspond to two minterms of distance 1 There is more than one way to construct a map. with this property,Karnaugh Maps,For a function of two variables say f x y. For a function of three variables say f x y z,For a function of four variables f w x y z. Logic Design Laboratory Manual 4,Realization of Boolean expression. 1 Y A B C D A BC D ABC D A B C D A B C D A B C D A B CD. After simplifying using K Map method we get Y A B C D. Realization using Basic gates TRUTH TABLE,INPUTS OUTPUT. Realization using NAND gates 0 1 0 1 0,Realization using NOR gates.
Logic Design Laboratory Manual 5, 2 For the given Truth Table realize a logical circuit using basic gates and NAND gates. Inputs Output,Check the components for their working. Insert the appropriate IC into the IC base,Make connections as shown in the circuit diagram. Provide the input data via the input switches and observe the output on output LEDs. Verify the Truth Table, RESULT Simplified and verified the Boolean function using basic gates and universal gates. VIVA QUESTIONS, 1 What are the different methods to obtain minimal expression.
2 What is a Min term and Max term,3 State the difference between SOP and POS. Logic Design Laboratory Manual 6,4 What is meant by canonical representation. 5 What is K map Why is it used,6 What are universal gates. EXPERIMENT 3 ADDERS AND SUBTRACTORS,AIM To realize. i Half Adder and Full Adder, ii Half Subtractor and Full Subtractor by using Basic gates and NAND gates.
LEARNING OBJECTIVE, To realize the adder and subtractor circuits using basic gates and universal gates. To realize full adder using two half adders, To realize a full subtractor using two half subtractors. COMPONENTS REQUIRED, IC 7400 IC 7408 IC 7486 IC 7432 Patch Cords IC Trainer Kit. Half Adder A combinational logic circuit that performs the addition of two data bits A and. B is called a half adder Addition will result in two output bits one of which is the sum bit. S and the other is the carry bit C The Boolean functions describing the half adder are. S A B C AB, Full Adder The half adder does not take the carry bit from its previous stage into account. This carry bit from its previous stage is called carry in bit A combinational logic circuit that. adds two data bits A and B and a carry in bit Cin is called a full adder The Boolean. functions describing the full adder are,S x y Cin C xy Cin x y.
Half Subtractor Subtracting a single bit binary value B from another A i e A B produces. a difference bit D and a borrow out bit B out This operation is called half subtraction and the. circuit to realize it is called a half subtractor The Boolean functions describing the half. Subtractor are,S A B C A B, Full Subtractor Subtracting two single bit binary values B Cin from a single bit value A. produces a difference bit D and a borrow out Br bit This is called full subtraction The. Boolean functions describing the full subtracter are. D x y Cin Br A B A Cin B Cin,Logic Design Laboratory Manual 7. I TO REALIZE HALF ADDER,TRUTH TABLE BOOLEAN EXPRESSIONS. INPUTS OUTPUTS,A B S C C A B,i Basic Gates ii NAND Gates. II FULL ADDER,TRUTH TABLE BOOLEAN EXPRESSIONS,INPUTS OUTPUTS.
A B Cin S C,0 0 0 0 0 C A B B Cin A Cin,i BASIC GATES. Logic Design Laboratory Manual 8,ii NAND GATES,III HALF SUBTRACTOR. TRUTH TABLE BOOLEAN EXPRESSIONS,INPUTS OUTPUTS D A B. A B D Br Br A B,Logic Design Laboratory Manual 9,i BASIC GATES ii NAND Gates. IV FULL SUBTRACTOR,TRUTH TABLE BOOLEAN EXPRESSIONS.
INPUTS OUTPUTS D A B C,A B Cin D Br Br A B B Cin A Cin. i BASIC GATES,Logic Design Laboratory Manual 10, ii To Realize the Full subtractor using NAND Gates only. Check the components for their working,Insert the appropriate IC into the IC base. Make connections as shown in the circuit diagram,Verify the Truth Table and observe the outputs. RESULT The truth table of the above circuits is verified. VIVA QUESTIONS,1 What is a half adder,2 What is a full adder.
3 What are the applications of adders,4 What is a half subtractor. 5 What is a full subtractor,6 What are the applications of subtractors. 7 Obtain the minimal expression for above circuits. 8 Realize a full adder using two half adders, 9 Realize a full subtractors using two half subtractors. Logic Design Laboratory Manual 11,EXPERIMENT 4 PARALLEL ADDER AND SUBTRACTOR. AIM To design and set up the following circuit using IC 7483. i A 4 bit binary parallel adder,ii A 4 bit binary parallel subtractor.
LEARNING OBJECTIVE,To learn about IC 7483 and its internal structure. To realize a subtractor using adder IC 7483,COMPONENTS REQUIRED. IC 7483 IC 7486 Patch Cords IC Trainer Kit, The Full adder can add single digit binary numbers and carries The largest sum that can be. obtained using a full adder is 112 Parallel adders can add multiple digit numbers If full. adders are placed in parallel we can add two or four digit numbers or any other size desired. Figure below uses STANDARD SYMBOLS to show a parallel adder capable of adding two. two digit binary numbers The addend would be on A inputs and the augend on the B inputs. For this explanation we will assume there is no input to C0 carry from a previous circuit. To add 102 addend and 012 augend the addend inputs will be 1 on A2 and 0 on A1 The. augend inputs will be 0 on B2 and 1 on B1 Working from right to left as we do in normal. addition let s calculate the outputs of each full adder With A1 at 0 and B1 at 1 the output of. adder1 will be a sum S1 of 1 with no carry C1 Since A2 is 1 and B2 is 0 we have a sum. S2 of 1 with no carry C2 from adder1 To determine the sum read the outputs C2 S2 and. S1 from left to right In this case C2 0 S2 1 and S1 1 The sum then of 102 and 012. Logic Design Laboratory Manual 12, is 0112 To add four bits we require four full adders arranged in parallel IC 7483 is a 4 bit. parallel adder whose pin diagram is shown,INPUTS A3 A2 A1 A0.
B3 B2 B1 B0,OUTPUT Cout S3 S2 S1 S0,IC 7483 pin diagram. i 4 Bit Binary Adder,An Example 7 2 11 1001,7 is realized at A3 A2 A1 A0 0111. 2 is realized at B3 B2 B1 B0 0010,ADDER CIRCUIT,Logic Design Laboratory Manual 13. Check all the components for their working,Insert the appropriate IC into the IC base. Make connections as shown in the circuit diagram,Apply augend and addend bits on A and B and cin 0.
Verify the results and observe the outputs,ii 4 BIT BINARY SUBTRACTOR. Subtraction is carried out by adding 2 s complement of the subtrahend. Example 8 3 5 0101,8 is realized at A3 A2 A1 A0 1000. 3 is realized at B3 B2 B1 B0 through X OR gates 0011. Output of X OR gate is 1 s complement of 3 1100,2 s Complement can be obtained by adding Cin 1. A3 A2 A1 A0 1 0 0 0,B3 B2 B1 B0 1 1 0 0,S3 S2 S1 S0 0 1 0 1. Cout 1 Ignored,Logic Design Laboratory Manual 14,Check all the components for their working.
Insert the appropriate IC into the IC base,Make connections as shown in the circuit diagram. Apply Minuend and subtrahend bits on A and B and cin 1. Verify the results and observe the outputs, RESULTS Verified the working of IC 7483 as adder and subtractor. EXPERIMENT 5 BCD TO EXCESS 3 CODE CONVERTERS, AIM To design and realize the following using IC 7483. I BCD to Excess 3 Code,II Excess 3 to BCD Code,LEARNING OBJECTIVE. To learn to realize BCD to Excess 3 code using adder IC 7483. To learn to realize Excess 3 to BCD Code using adder IC 7483. COMPONENTS REQUIRED,IC 7483 IC 7486 Patch Cords IC Trainer Kit.
Logic Design Laboratory Manual 2 integrated circuit chips available TTL ICs are usually distinguished by numerical designation as the 5400 and 7400 series PROCEDURE 1 Check the components for their working 2 Insert the appropriate IC into the IC base 3 Make connections as shown in the circuit diagram

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