Introduction to Digital Combinational Logic and Systems

Introduction To Digital Combinational Logic And Systems-Free PDF

  • Date:30 Jun 2020
  • Views:2
  • Downloads:0
  • Pages:26
  • Size:342.63 KB

Share Pdf : Introduction To Digital Combinational Logic And Systems

Download and Preview : Introduction To Digital Combinational Logic And Systems

Report CopyRight/DMCA Form For : Introduction To Digital Combinational Logic And Systems


Signal V Signal V Signal V,8 8 Level 7,6 6 Level 5. 2 2 Level 2, 0 2 3 4 5 6 7 Time 0 2 3 4 5 6 7 Time 0 2 3 4 5 6 7 Time. Figure 2 Schematic representation of analog and digital signals. This review should have motivated us to ask a few questions about these signals and in. particular about the digital signal shown on Figure 2c. Some of these questions are, 1 How is the information embodied by the digital signal represented. 2 How is the signal generated, a How is the sampling frequency selected and how is it related to the quality. of signal representation,b How is the amplitude quantization achieved.
3 What are the advantages and disadvantages of generating the digital signal For. example how does it perform in,a Accuracy,b Transmission. c Noise immunity,d Information storage,e Computation. In the next few classes we will answer these questions and explore the fundamental issues. associated with the design of digital circuits,6 071 22 071 Spring 2006 Chaniotakis and Cory 2. Numbering Systems,Binary Code, In digital electronics the signals are formed with only two voltage values HI and LOW or. level 1 and level 0 and it is called binary digital signal 1 Therefore the information. contained in the digital signal is represented by the numbers 1 and 0 In most digital. systems the state 1 corresponds to a voltage range from 2V to 5V while the state 0. corresponds to a voltage range from a fraction of a volt to 1 volts. Digital operations are performed by creating and operating on binary numbers Binary. numbers are comprised of the digits 0 and 1 and are based on powers of 2. Each digit of a binary number 0 or 1 is called a bit an abbreviation for binary digit Four. bits together is a nibble 8 bits is called a byte 8 16 32 64 bit arrangements are also. called words The rightmost bit is called the Least Significant Bit LSB while the leftmost. bit is called the Most Significant Bit MSB The schematic below illustrates the general. structure of a binary number and the associated labels. N 1101 0110 1010,MSB word LSB, In addition to binary digital systems and its associated binary logic multivalued logic also exists but we will.
not consider it in our discussion,6 071 22 071 Spring 2006 Chaniotakis and Cory 3. Binary to Decimal Conversion, The conversion of a binary number to a decimal number may be accomplished by taking. the successive powers of 2 and summing for the result. For example let s consider the four bit binary number 0101 The conversion to a decimal. number base 10 is illustrated below,0 4 0 1 510, For this four bit binary number the range of powers of 2 goes from 0 corresponding to the. LSB to 3 corresponding to the MSB The number 5 is shown as 510 to indicate that it is a. decimal number power of 10, The signal represented on Figure 2c has a value of 5 V at time 6 The binary. representation of that value is 0101 and it is shown on Figure 3 replacing Level 4 We will. see more of this later when we consider the fundamentals of the device which converts the. analog signal to a digital signal,0 2 3 4 5 6 7 Time.
In the next few examples we will use the subscript 2 to indicate a binary number but the. subscripts will be omitted after that,6 071 22 071 Spring 2006 Chaniotakis and Cory 4. Verify the Binary to Decimal conversion,11112 1510. 1111 00002 24010,1111 11112 25510,1101 10112 21910. 0001 0101 10112 34710,1001 0101 10112 239510,Decimal to Binary Conversion. The conversion of a decimal number to a binary number is accomplished by successively. dividing the decimal number by 2 and recording the remainder as 0 or 1 Here is an. example of the conversion of decimal number 125 to binary. 2 0111 1101, Practice number conversion by verifying the conversions from decimal to binary.
Decimal Binary,69 0100 0101,299 0001 0010 1011,756 0010 1111 0100. 6 071 22 071 Spring 2006 Chaniotakis and Cory 5,Representation of fractions and signed numbers. A fractional number may be represented as a binary fraction by simply extending the. procedure used in representing integer numbers For example. 13 7510 1101 11002, The procedure is clearly visualized by considering the following mapping. 23 22 21 20 2 1 2 2 2 3 2 4,8 4 2 1 0 5 0 25 0 125 0 0625. 1 1 0 1 1 1 0 0, Signed binary numbers may be represented by assigning the MSB to indicate the sign A 0.
is used to indicate a positive number and a 1 is used to indicate a negative number. For example an 8 bit signed binary number represents the decimal numbers from 128 to. Two s complement is used to represent negative numbers The use of 2 s complement. simplifies the operation of subtraction since the circuit is only required to perform the. operation of addition since X Y X Y, The 2 s complement of a binary number is obtained by subtracting each digit of the binary. number from digit 1 This is equivalent to replacing all 1 s by 0 s and all 0 s by 1 s. Negative numbers of 2 s compliment can then be found by adding 1 to the complement of a. positive number, For example the 2 s complement of the 8 bit binary number 0000 1110 is. 1111 0001 1010, The negative number of this 2 s complement representation is. 1111 0110 1010,The procedure is outlined in the following. 0 0 0 0 1 0 1 0 binary number 1010,1 1 1 1 0 1 0 1 2 s complement.
1 1 1 1 0 1 1 0 1010,6 071 22 071 Spring 2006 Chaniotakis and Cory 6. By adding the two numbers the result is zero as shown below. 0000 1110 10,1111 0110 10,0000 0000 0, The table below shows the 2 s complement representation of a few numbers Fill in the. empty spaces,Decimal 2 s complement,0 0000 0000,1 1111 1111. 2 1111 1110,3 1111 1101,4 1111 1100,10 1111 0110,Binary Coded Decimal BCD Code. BCD is a code used to represent each digit of a decimal number 0 to 9 as a 4 bit binary. For example the decimal number 260 corresponds to the BDC number 0010 0110 0000. 2N 6N 0N Decimal,0010 0110 0000 BDC, This code is used to drive the 7 segment led displays.
For example the BCD number 0010 corresponds to decimal 2 and is used to drive the. segments a b d e g of the display Similarly the number 0110 corresponds to number 6 and. it is used to drive segments a c d e f g BCD 0000 corresponds to decimal 0 and it drives. 6 071 22 071 Spring 2006 Chaniotakis and Cory 7, segments a b c d e f Special logic ICs are available for driving the led segments from a. BCD number,Numbers with other bases, The octal system with base 8 and digits 0 1 2 3 4 5 6 7 and the hexadecimal system with. base 16 and digits 0 1 2 3 4 5 6 7 8 9 A B C D E F are also used in digital electronics Octal. and Hex representation is more compact consider the conversion of the decimal number. 1132 in binary Octal and Hex shown below and it is used in assembly language. programming of microcontrollers,113210 0100 0110 11002 21548 46C16. 6 071 22 071 Spring 2006 Chaniotakis and Cory 8,Fundamental Digital Devices The inverter. The fundamental digital circuit for performing binary operations is the one which will. convert from a logic 1 to a logic 0 and vise versa In our discussions we will use the. positive logic convention which implies that the logic level 1 will correspond to the higher. voltage level and the logic level 0 will correspond to the lower voltage level Such a. fundamental is shown on Figure 4,Vi 3 terminal,Figure 4 Fundamental inverter circuit.
The ideal voltage transfer characteristic of this circuit is shown on Figure 5. Figure 5 Ideal inverter voltage transfer characteristic. When the input voltage exceeds the transition value Vtr the output switches. 6 071 22 071 Spring 2006 Chaniotakis and Cory 9, It will become useful to familiarize ourselves with time evolution of digital signals Such. representation is called timing diagram which is used extensively in representing the. operation of digital circuits For our idealized inverter circuit also called inverter gate a. timing diagram would look like,Vi 0 0 0 0,Figure 6 Ideal inverter timing diagram. We thus see that the inverter is a voltage controlled digital switch In practice the behavior. of the inverter is not ideal The output could assume a low value which will be in a range of. voltages and a high value which also encompasses a range of voltage values In addition. the transition occurs with a time delay, The inverter circuit may be constructed with active devices such as the Field Effect. Transistor FET or the Bipolar Junction Transistor BJT The inverter circuit. arrangements for these fundamental devices are shown on Figure 7. Id Ic Vi Vo Inverter symbol,Vi M Vi Q1 showing high Vc. and low ground,Inverter Inverter Vi Vo,Implementation Implementation CMOS inverter 2.
with a FET with a BJT,Inverter Symbol,Figure 7 Inverter circuits and inverter symbol. The Complementary Metal Oxide Semiconductor CMOS inverter incorporates an n channel and a p. channel MOSFET,6 071 22 071 Spring 2006 Chaniotakis and Cory 10. The output voltage is the inverse of the input and the switching from one state to another. state happens when the input voltage crosses a certain value Vtr An inverter with supply. voltages Vc and Ve and the corresponding voltage transfer characteristic is. Ve Ve Vtr Vc Vi, When Vi is less than the voltage Vtr i e when Vi is low the output is VH high As the. input voltage exceeds Vtr Vi is now high the output switches to VL low Note that the. values for VH and VL are not the same as the supply rails of the device The actual values. of VH and VL depend on the particular technology used in the construction of the inverter. For each design and for the particular semiconductor technology used the supply voltages. Vc and Ve are well defined A familiar power supply for digital systems is the Vc 5V. and Ve 0V Supply systems with Vc voltage levels ranging from 1 5V to 5V are. Ve Vtr Vc Vi,Vi low 0 Vi high 1, In practical circuits the transition from one state to another does not happen abruptly The. transition is gradual and there is not a single value at which the transitions happen but. 6 071 22 071 Spring 2006 Chaniotakis and Cory 11, rather a range of values that correspond to the transition as well as to the high and low.
states This is a desirable situation since it allows for the design of robust systems with. considerable noise immunity, In addition there is a range of values which correspond to a certain logic level Figure 8. shows a generic representation of the logic levels. Logic Level 1,Indeterminate,Forbidden Region,Logic Level 0. Figure 8 Logic gate levels, Any value less than VH min and greater than VL max falls in the forbidden region and its. state is indeterminate The values for VH min and VL max are different for the input and. output of a gate It is important to pay particular attention to these voltage levels since. when one gate drives another the input and output of each should fall within the specified. level values, When one gate drives another as in the graphic shown on Figure 9 the various voltage. levels are defined as follows, VHin min The minimum voltage level required for a logic level 1 at the input.
VLin max The maximum voltage level required for a logic 0 at the input of a. VHout min The minimum voltage level required for a logic level 1 at the output. VLout max The maximum voltage level required for a logic 0 at the output of a. 6 071 22 071 Spring 2006 Chaniotakis and Cory 12,Logic Level 1. VHout min Logic Level 1,Noise margin HI VNMH,Indeterminate Indeterminate. Noise margin LO VNML,VLout max Logic Level 0,Logic Level 0. Figure 9 Logic gate input and output voltage levels. As can be seen from Figure 9 the presence of noise at the output of a certain gate may. result in a voltage level which may be recognized as an appropriate state at the input of the. following gate The maximum voltage deviations due to noise that can be accepted by the. logic gate inputs are defined as the HI and LO voltage noise margins. VNMH V1out min V1in min,VNML V0in max V0out max,These voltage levels are summarized on Figure 10. Noise margin H,Sender Indeterminate,Noise margin L.
Figure 10 Voltage levels for sender and receiver, The actual values of the minimum and maximum voltage values at the input and output of. the logic gates depend on the type of device used to construct the logic gate Currently. there are two dominant logic families They are the Transistor to Transistor Logic TTL. based on the BJT inverter shown on Figure 7 and the Complementary Metal Oxide. Semiconductor CMOS based on the MOS families Besides differences in speed and. power consumption these logic families are also different in the acceptable logic voltage. levels for the gates These differences should be taken into consideration when the design. involves interfacing between TTL and CMOS circuits. 6 071 22 071 Spring 2006 Chaniotakis and Cory 13, Table I provides a general comparison of the two families. Supply voltage V 5 5,V1in min 2 3 5,V0in max 0 8 1 5. V1out min 2 4 4 5,V0out max 0 4 0 1,VNMH 0 4 1 0,VNML 0 4 1 4. Table I Comparison of TTL and CMOS logic family parameters. A few words on power consumption,Let s consider the inverting gate.
The capacitor C represents the wiring capacitance as well as the capacitance of the gate. Introduction to Digital Combinational Logic and Systems Design So far we have been discussing the generation transmission and processing of signals whose amplitude voltage current varies continuously in time and can in principle take any value At a certain instant of time we may represent a signal by displaying its amplitude in an analog form or in a digital format The graphics below

Related Books