DESIGNING SEQUENTIAL LOGIC CIRCUITS

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chapter7 pub fm Page 271 Wednesday November 22 2000 8 41 AM. Section 271,7 8 1Latch vs Register Based Pipelines. 7 8 2NORA CMOS A Logic Style for Pipelined Structures. 7 9 Non Bistable Sequential Circuits,7 9 1The Schmitt Trigger. 7 9 2Monostable Sequential Circuits,7 9 3Astable Circuits. 7 10 Perspective Choosing a Clocking Strategy,7 11 Summary. 7 12 To Probe Further,7 13 Exercises and Design Problems.
chapter7 pub fm Page 272 Wednesday November 22 2000 8 41 AM. 272 DESIGNING SEQUENTIAL LOGIC CIRCUITS Chapter 7,7 1 Introduction. Combinational logic circuits that were described earlier have the property that the output. of a logic block is only a function of the current input values assuming that enough time. has elapsed for the logic gates to settle Yet virtually all useful systems require storage of. state information leading to another class of circuits called sequential logic circuits In. these circuits the output not only depends upon the current values of the inputs but also. upon preceding input values In other words a sequential circuit remembers some of the. past history of the system it has memory, Figure 7 1 shows a block diagram of a generic finite state machine FSM that con. sists of combinational logic and registers that hold the system state The system depicted. here belongs to the class of synchronous sequential systems in which all registers are. under control of a single global clock The outputs of the FSM are a function of the current. Inputs and the Current State The Next State is determined based on the Current State and. the current Inputs and is fed to the inputs of registers On the rising edge of the clock the. Next State bits are copied to the outputs of the registers after some propagation delay. and a new cycle begins The register then ignores changes in the input signals until the. next rising edge In general registers can be positive edge triggered where the input data. is copied on the positive edge or negative edge triggered where the input data is copied. on the negative edge of the clock as is indicated by a small circle at the clock input. Inputs Outputs,COMBINATIONAL,Current State Next State. Figure 7 1 Block diagram of a finite state machine using positive edge triggered registers. This chapter discusses the CMOS implementation of the most important sequential. building blocks A variety of choices in sequential primitives and clocking methodologies. exist making the correct selection is getting increasingly important in modern digital cir. cuits and can have a great impact on performance power and or design complexity. Before embarking on a detailed discussion on the various design options a revision of the. design metrics and a classification of the sequential elements is necessary. 7 2 Timing Metrics for Sequential Circuits, There are three important timing parameters associated with a register as illustrated in Fig. ure 7 2 The set up time tsu is the time that the data inputs D input must be valid before. the clock transition this is the 0 to 1 transition for a positive edge triggered register The. hold time thold is the time the data input must remain valid after the clock edge Assum. chapter7 pub fm Page 273 Wednesday November 22 2000 8 41 AM. Section 7 3 Classification of Memory Elements 273,t Register.
tsu thold D Q,D DATA CLK,Figure 7 2 Definition of set up. Q DATA time hold time and propagation,STABLE t delay of a synchronous register. ing that the set up and hold times are met the data at the D input is copied to the Q output. after a worst case propagation delay with reference to the clock edge denoted by tc q. Given the timing information for the registers and the combination logic some sys. tem level timing constraints can be derived Assume that the worst case propagation. delay of the logic equals tplogic while its minimum delay also called the contamination. delay is tcd The minimum clock period T required for proper operation of the sequential. circuit is given by,T t c q t p log ic t su 7 1, The hold time of the register imposes an extra constraint for proper operation. t cdregister t cdlogic t hold 7 2, where tcdregister is the minimum propagation delay or contamination delay of the register. As seen from Eq 7 1 it is important to minimize the values of the timing parame. ters associated with the register as these directly affect the rate at which a sequential cir. cuit can be clocked In fact modern high performance systems are characterized by a. very low logic depth and the register propagation delay and set up times account for a. significant portion of the clock period For example the DEC Alpha EV6 microprocessor. Gieseke97 has a maximum logic depth of 12 gates and the register overhead stands for. approximately 15 of the clock period In general the requirement of Eq 7 2 is not hard. to meet although it becomes an issue when there is little or no logic between registers or. when the clocks at different registers are somewhat out of phase due to clock skew as will. be discussed in a later Chapter,7 3 Classification of Memory Elements.
Foreground versus Background Memory, At a high level memory is classified into background and foreground memory Memory. that is embedded into logic is foreground memory and is most often organized as individ. ual registers of register banks Large amounts of centralized memory core are referred to. as background memory Background memory discussed later in this book achieves. chapter7 pub fm Page 274 Wednesday November 22 2000 8 41 AM. 274 DESIGNING SEQUENTIAL LOGIC CIRCUITS Chapter 7, higher area densities through efficient use of array structures and by trading off perfor. mance and robustness for size In this chapter we focus on foreground memories. Static versus Dynamic Memory, Memories can be static or dynamic Static memories preserve the state as long as the. power is turned on Static memories are built using positive feedback or regeneration. where the circuit topology consists of intentional connections between the output and the. input of a combinational circuit Static memories are most useful when the register won t. be updated for extended periods of time An example of such is configuration data loaded. at power up time This condition also holds for most processors that use conditional clock. ing i e gated clocks where the clock is turned off for unused modules In that case there. are no guarantees on how frequently the registers will be clocked and static memories are. needed to preserve the state information Memory based on positive feedback fall under. the class of elements called multivibrator circuits The bistable element is its most popu. lar representative but other elements such as monostable and astable circuits are also fre. quently used, Dynamic memories store state for a short period of time on the order of millisec. onds They are based on the principle of temporary charge storage on parasitic capacitors. associated with MOS devices As with dynamic logic discussed earlier the capacitors. have to be refreshed periodically to annihilate charge leakage Dynamic memories tend to. simpler resulting in significantly higher performance and lower power dissipation They. are most useful in datapath circuits that require high performance levels and are periodi. cally clocked It is possible to use dynamic circuitry even when circuits are conditionally. clocked if the state can be discarded when a module goes into idle mode. Latches vs Registers, A latch is an essential component in the construction of an edge triggered register It is.
level sensitive circuit that passes the D input to the Q output when the clock signal is high. This latch is said to be in transparent mode When the clock is low the input data sampled. on the falling edge of the clock is held stable at the output for the entire phase and the. latch is in hold mode The inputs must be stable for a short period around the falling edge. of the clock to meet set up and hold requirements A latch operating under the above con. ditions is a positive latch Similarly a negative latch passes the D input to the Q output. when the clock signal is low The signal waveforms for a positive and negative latch are. shown in Figure 7 3 A wide variety of static and dynamic implementations exists for the. realization of latches, Contrary to level sensitive latches edge triggered registers only sample the input on. a clock transition 0 to 1 for a positive edge triggered register and 1 to 0 for a negative. edge triggered register They are typically built using the latch primitives of Figure 7 3 A. most often recurring configuration is the master slave structure that cascades a positive. and negative latch Registers can also be constructed using one shot generators of the. clock signal glitch registers or using other specialized structures Examples of these. are shown later in this chapter, chapter7 pub fm Page 275 Wednesday November 22 2000 8 41 AM. Section 7 4 Static Latches and Registers 275,Positive Latch Negative Latch. In D Q Out In D Q Out,Out Out Out Out,stable follows In stable follows In. Figure 7 3 Timing of positive and negative latches. 7 4 Static Latches and Registers,7 4 1 The Bistability Principle.
Static memories use positive feedback to create a bistable circuit a circuit having two. stable states that represent 0 and 1 The basic idea is shown in Figure 7 4a which shows. two inverters connected in cascade along with a voltage transfer characteristic typical of. such a circuit Also plotted are the VTCs of the first inverter that is Vo1 versus Vi1 and the. second inverter Vo2 versus Vo1 The latter plot is rotated to accentuate that Vi2 Vo1. Assume now that the output of the second inverter Vo2 is connected to the input of the first. Vi1 as shown by the dotted lines in Figure 7 4a The resulting circuit has only three possi. Vi1 Vo1 Vi2,Figure 7 4 Two cascaded inverters a B,and their VTCs b. chapter7 pub fm Page 276 Wednesday November 22 2000 8 41 AM. 276 DESIGNING SEQUENTIAL LOGIC CIRCUITS Chapter 7, ble operation points A B and C as demonstrated on the combined VTC The following. important conjecture is easily proven to be valid, Under the condition that the gain of the inverter in the transient region is larger than 1 only A. and B are stable operation points and C is a metastable operation point. Suppose that the cross coupled inverter pair is biased at point C A small deviation from. this bias point possibly caused by noise is amplified and regenerated around the circuit. loop This is a consequence of the gain around the loop being larger than 1 The effect is. demonstrated in Figure 7 5a A small deviation is applied to Vi1 biased in C This devi. ation is amplified by the gain of the inverter The enlarged divergence is applied to the sec. ond inverter and amplified once more The bias point moves away from C until one of the. operation points A or B is reached In conclusion C is an unstable operation point Every. deviation even the smallest one causes the operation point to run away from its original. bias The chance is indeed very small that the cross coupled inverter pair is biased at C. and stays there Operation points with this property are termed metastable. Vi1 Vo2 Vi1 Vo2,Figure 7 5 a,Metastability b, On the other hand A and B are stable operation points as demonstrated in Figure. 7 5b In these points the loop gain is much smaller than unity Even a rather large devi. ation from the operation point is reduced in size and disappears. Hence the cross coupling of two inverters results in a bistable circuit that is a cir. cuit with two stable states each corresponding to a logic state The circuit serves as a. memory storing either a 1 or a 0 corresponding to positions A and B. In order to change the stored value we must be able to bring the circuit from state A. to B and vice versa Since the precondition for stability is that the loop gain G is smaller. than unity we can achieve this by making A or B temporarily unstable by increasing G to. a value larger than 1 This is generally done by applying a trigger pulse at Vi1 or Vi2 For. instance assume that the system is in position A Vi1 0 Vi2 1 Forcing Vi1 to 1 causes. both inverters to be on simultaneously for a short time and the loop gain G to be larger. than 1 The positive feedback regenerates the effect of the trigger pulse and the circuit. moves to the other state B in this case The width of the trigger pulse need be only a little. chapter7 pub fm Page 277 Wednesday November 22 2000 8 41 AM. Section 7 4 Static Latches and Registers 277, larger than the total propagation delay around the circuit loop which is twice the average.
propagation delay of the inverters, In summary a bistable circuit has two stable states In absence of any triggering the. circuit remains in a single state assuming that the power supply remains applied to the. circuit and hence remembers a value A trigger pulse must be applied to change the state. of the circuit Another common name for a bistable circuit is flip flop unfortunately an. edge triggered register is also referred to as a flip flop. 7 4 2 SR Flip Flops, The cross coupled inverter pair shown in the previous section provides an approach to. store a binary variable in a stable way However extra circuitry must be added to enable. control of the memory states The simplest incarnation accomplishing this is the well. 7 13 Exercises and Design Problems chapter7 pub fm Page 271 Wednesday November 22 2000 8 41 AM 272 DESIGNING SEQUENTIAL LOGIC CIRCUITS Chapter 7 7 1 Introduction Combinational logic circuits that were described earlier have the property that the output of a logic block is only a function of thecurrent input values assuming that enough time has elapsed for the logic gates to settle Yet

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