DESIGN AND IMPLEMENTATION OF EFFICIENT ADDER USING VARIOUS

Design And Implementation Of Efficient Adder Using Various-Free PDF

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International Research Journal of Engineering and Technology IRJET e ISSN 2395 0056. Volume 05 Issue 02 Feb 2018 www irjet net p ISSN 2395 0072. 1 1 Proposed method Conventional MUX based full adder using GDI Cell. GDI Cell To reduce the power and area the conventional full adder in. reduction phase of multiplier or any other processor is. A Gate Diffusion Input 4 is a technique for low power digital replaced by a modified full adder The modified full adder. circuit design in an embedded system This technique is used circuits consist of 2 1 MUX and XOR gate One XOR gate in. to reduce power consumption area delay This technique is the conventional full adder is replaced by a multiplexer block. used to reduce the number of transistors compared to so that the delay path is minimized. conventional CMOS design,DELAY XOR MUX, This can be implemented using second MUX with XOR output. as a selection line Since XOR involves most of the power. consumption in adder circuits by reducing the number of. XOR gates power consumptions of the full adder can be. reduced This type of adder is employed in the multiplier. and so the efficiency is increased,Figure 2 Basic GDI Cell. P G Out Function,0 B A AB F1,B 1 A A B F2,1 B A A B OR Figure 4 MUX Based Full Adder. B 0 A AB AND,The operation of adder is,C B A AB AC MUX. 0 1 A A NOT 1 When both A and B are Zero or One SUM C. 2 When either of A or B is One and another is Zero SUM. Table 1 Boolean function of GDI cell C,3 When both A and B are Zero or One CARRY A.
EXOR DESIGN USING GDI CELL 4 When either of A or B is One and another is Zero CARRY. When compared with other technologies GDI, technology can reduce the number of transistor in this a Pass Transistor Logic using GDI Cell. ex or design, In electronics pass transistor logic describes various logic. families used in the design of integrated circuits Pass. transistor logic is used to enhance the performance of. arithmetic and logic circuits This logic can be used to reduce. the count of transistors used to make different logic gates by. excluding redundant transistors, The pass transistor logic is used to reduce the number of. transistors used when compared to CMOS design in the. realization of complex systems When the number of a. transistor is decreased the CHIP area also decreases parallel. When the number of a transistor is reduced we can easily. decrease the number of layout elements The pass transistor. logic design can be used to remove some transistor and it. may be important to reduce the power consumption,Figure 3 EX OR using GDI cell. 2018 IRJET Impact Factor value 6 171 ISO 9001 2008 Certified Journal Page 270. International Research Journal of Engineering and Technology IRJET e ISSN 2395 0056. Volume 05 Issue 02 Feb 2018 www irjet net p ISSN 2395 0072. Binary input A Binary input B Carry,A0 00001111 B0 0.
00110011 10010011,01010101 01010101,10010011 10101010. 10101010 10010011,Figure 5 Pass Transistor Logic A5 B5 0. 01010101 01010101,b 2 T Logic using GDI Cell 10010011 00110011. The 2 T logic 5 design which is a combination of both PMOS 01010001 00001111. and NMOS This logic is also known as CMOS logic The 2 T. logic is combined in a specific manner to get a full adder with TABLE 1 The truth table for Ripple Carry Adder. SUM and CARRY output RCA, This logic is very efficient when compared to MUX based full The following truth table which consists of input from. adder and pass transistor logic A0 A7 AND B0 B7 the output S0 S7 is as follows. Figure 6 2 T Logic,1 1 Proposed method ripple carry adder.
In this paper we have designed an 8 bit ripple carry adder The above Figure shows the output for the first four inputs. using different logic styles such as pass transistor logic mux from a0 to a3 when added with the second four inputs b0 to. based logic and 2T logic An 8 bit ripple carry adder can be b3 respectively. built by using eight 1 bit full adders The Ripple carry adder. creates a logic circuit using multiple full adders to add N bit. Figure 9 Output for Ripple Carry Adder, 2018 IRJET Impact Factor value 6 171 ISO 9001 2008 Certified Journal Page 271. International Research Journal of Engineering and Technology IRJET e ISSN 2395 0056. Volume 05 Issue 02 Feb 2018 www irjet net p ISSN 2395 0072. The above Figure 9 shows the output for the first four inputs. from a4 to a7 when added with the second four inputs b4 to. b7 respectively,2 Performance Comparison,Name Of The Design Number of Delay ns. transistors,Conventional MUX based full 28 34 8,Proposed Pass Transistor 14 22. Logic 1 bit,Proposed 2 T Logic 1 bit 10 19,Conventional MUX based 224 32. Proposed Pass Transistor 112 24, Proposed 2 T RCA 8 bit 80 22 Figure 11 Pass transistor based full adder design.
The above table is used to compare the full adder designs. that have been implemented using various logics The. various parameters such as some transistors and the time. taken will be compared,3 Simulation Results, Figure 11 1 Pass Transistor based full adder output. Figure 10 MUX based full adder design,Figure 12 2 T full adder design. Figure 10 1 MUX based full adder output, 2018 IRJET Impact Factor value 6 171 ISO 9001 2008 Certified Journal Page 272. International Research Journal of Engineering and Technology IRJET e ISSN 2395 0056. Volume 05 Issue 02 Feb 2018 www irjet net p ISSN 2395 0072. Electronics Electrical Computer Science Applications of. Engineering Technology Volume 2 Issue 4 July 2014 PP. 5 N Srinivasan Rao B Vijayasree Design the 2 1 MUX. with 2T Logic and comparing the Power Dissipation and. Area with different logics IJAREEIE Vo1 4 Issue 3 March. 6 S Srikanth I Thahirabanu Low Power Array Multiplier. using Modified Full Adder 2nd IEEE ICETECH 7th and 18th. March 2016 Coimbatore TN India,Figure 12 1 2 T full adder output. 3 CONCLUSIONS, In the project work the full adder design is realized in three.
different logic styles with the help of MUX based full adder. pass transistor logic and 2 T logic In this project work by. using the obtained output for a 1 bit adder the 8 bit adder. has been designed and tested successfully and the output is. displayed In the future we will focus on various other logic. designs which will provide a further improvement over. various parameter and hence resulting in higher level of. efficiency The required logic can be realized within a. smaller area when compared to the conventional full adder. design Simulation results show that this proposed full adder. achieves better improvement regarding area and time delay. when compared with other full adders,REFERENCES, 1 Hung Tien Bui Yuke Wang and Yingatao Jiang Design. and Analysis of Low Power 10 Transistor full Adders Using. Novel XOR XNOR Gates IEEE transactions on circuits and. systems ii analog and digital signal processing Vol 49 No 1. January 2002, 2 Aditya Kumar Singh Bishnu Prasad De Santanu Maity. Design and Comparison of Multipliers Using Different Logic. Styles International Journal of Soft Computing and. Engineering IJSCE ISSN 2231 2307 volume 2 Issue 2, 3 Shen Fu Hsiao Ming Roun Jiang Jia Sien Yeh Design of. highspeed low power 3 2counter and 4 2 compressor for. fast multipliers IEEE Electronics Letters 19th February. 1998 Vol 34 No 4 ISSN 0013 5194,4 Jashanpreet Kaur Navdeep Kaur and Amit Grover A. review on gate diffusion input GDI in International Journal. of Advance Research in, 2018 IRJET Impact Factor value 6 171 ISO 9001 2008 Certified Journal Page 273.
the conventional full adder is replaced by a multiplexer block so that the delay path is minimized DELAY XOR MUX This can be implemented using second MUX with XOR output as a selection line Since XOR involves most of the power consumption in adder circuits by reducing the number of XOR gates power consumptions of the full adder can be

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