By Ian Collins Analog Devices

By Ian Collins Analog Devices-Free PDF

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90 Loop Filter,IN 100 VCO,Phase Noise dBc Hz,Figure 4 A PFD out of phase and frequency lock. 100 1k 10k 100k 1M 10M 100M,Frequency Hz,Figure 8 Total PLL noise. Figure 5 Phase frequency detector frequency and phase lock As can be seen with the ADIsimPLL plots shown the noisy phase noise. profile of the REFIN Figure 6 is filtered by the low pass filter All the. Returning to our original example of the noisy clock that requires cleaning. in band noise contributed by the PLL reference and PFD circuitry is. the phase noise profile of the clock free running VCXO and closed loop. filtered out by the low pass filter leaving only the much lower VCXO. PLL can be modeled in ADIsimPLL, noise Figure 7 outside the loop bandwidth Figure 8 When the output. 80 frequency is equal to the input frequency it creates one of the simplest. PLL configurations Such a PLL is called a clock clean up PLL For clock. 90 clean up applications such as these narrow 1 kHz low pass filter. bandwidths are recommended,SSB Phase Noise dBc Hz,110 High Frequency Integer N Architecture. To generate a range of higher frequencies a VCO is used which tunes over. a wider range than a VCXO This is regularly used in frequency hopping. 130 or in spread spectrum frequency hopping FHSS applications In such. PLLs the output is a high multiple of the reference frequency Voltage. controlled oscillators contain a variable tuning element such as a varactor. diode which varies its capacitance with input voltage allowing a tuneable. resonant circuit which permits a range of frequencies to be generated. 160 Figure 9 The PLL can be thought of as a control system for this VCO. 100 1k 10k 100k 1M 10M 100M,Offset Frequency Hz, A feedback divider is used to divide the VCO frequency to the PFD.
Figure 6 Reference noise frequency which allows a PLL to generate output frequencies that are. multiples of the PFD frequency A divider may also be used in the refer. ence path which permits higher frequency references to be used than. 90 the PFD frequency A PLL like this is the ADF4108 from Analog Devices. The PLL counters are the second essential element to be considered in. 100 our circuit,SSB Phase Noise dBc Hz,VCO Output Frequency MHz. 100 1k 10k 100k 1M 10M 100M,Offset Frequency Hz V,Figure 7 Free running VCXO. VCO Tuning Voltage V,Figure 9 Voltage controlled oscillator. 2 Analog Dialogue 52 07 July 2018, The key performance parameters of PLLs are phase noise unwanted Table 1 Dual Modulus Prescaler Operation. by products of the frequency synthesis process or spurious frequencies. spurs for short For integer N PLLs spurious frequencies are generated N Value P P 1 B Value A Value. by the PFD frequency A leakage current from the charge pump will modu 90 9 11 2. late the tuning port of the VCO This effect is lessened by the low pass filter. and the narrower this is the greater the filtering of the spurious frequency 81 9 10 1. An ideal tone would have no noise or additional spurious frequency 72 8 9 0. Figure 10 but in practice phase noise appears as a skirtaround a carrier. as shown in Figure 11 Single sideband phase noise is the relative noise. power to the carrier in a 1 Hz bandwidth specified at a frequency offset 56 8 7 0. from the carrier 48 8 6 0,No Unwanted Discrete Tones.
No Noise That Is Spurs 0 8 0 0,Fc Carrier Frequency. Figure 10 Ideal LO spectrum The in band inside the PLL loop filter bandwidth phase noise is directly. influenced by the value of N and in band noise is increased by 20log. N So for narrow band applications in which the N value is high the. PS in band noise is dominated by the high N value A system that permits. a much lower N value but still permits fine resolution is enabled by a. fractional N synthesizer such as the ADF4159 or HMC704 In this manner. SC f PSSB PS, the in band phase noise can be greatly reduced Figures 13 through 16. illustrate how this is achieved In these examples two PLLs are used to. generate frequencies suitable for a 5G systems local oscillator LO in. a range between 7 4 GHz to 7 6 GHz with 1 MHz of channel resolution. The ADF4108 is used in an integer N configuration Figure 13 and the. f0 f HMC704 is used in a fractional N configuration The HMC704 Figure 14. Frequency can be used with a 50 MHz PFD frequency which lowers the N value and. Figure 11 Single sideband phase noise hence the in band noise while still permitting a 1 MHz or indeed smaller. frequency step size an improvement of 15 dB at 8 kHz offset frequency. Integer N and Fractional N Divider is noted Figure 15 vs Figure 16 The ADF4108 however is forced to use. a 1 MHz PFD to achieve the same resolution, For narrow band applications the channel spacing is narrow typically. 5 MHz and the feedback counter N is high Gaining high N values with a Care needs to be taken with fractional N PLLs to ensure that spurious. small circuit is achieved by the use of a dual modulus P P 1 prescaler as tones do not degrade system performance On PLLs such as the HMC704. seen in Figure 12 and allows N values to be computed with the calculation integer boundary spurs generated when the fractional portion of the N. of N PB A which using the example of an 8 9 prescaler and an N value approaches 0 or 1 like 147 98 or 148 02 are very close to the integer. value of 90 computes a value of 11 for B and 2 for A The dual modulus value of 148 generate the most concern This can be mitigated by buffering. prescaler will divide by 9 for A or two cycles It will then divide by 8 for the VCO output to the RF input and or careful frequency planning in which. the remaining B A or 9 cycles as described in Table 1 The prescaler is the REFIN can be changed to avoid these more problematic frequencies. generally designed using a higher frequency circuit technology such as. bipolar emitter coupled logic ECL circuits while the A and B counters Loop Bandwidth FPFD 10. can take this lower frequency prescaler output and can be manufactured 1 MHz 7400 MHz. with lower speed CMOS circuitry This reduces circuit area and power Charge. consumption Low frequency clean up PLLs like the ADF4002 omit 1 MHz Pump. this prescaler,FREF Reference F1,Low N 7400,Divider Phase N 7401. R Pass VCO FOUT N,B Figure 13 Integer N PLL,Load Loop Bandwidth FPFD 10.
Load 50 MHz,VCO 7400 MHz,A Charge 7401 MHz,Control FPFD PFD. Counter Low P 50 MHz Pump,Dual Modulus,P P 1 N 148 0 50. Total Number of Counts of FOUT in a Full F1 Cycle N 148 1 50. A P 1 B A P N,AP A BP AP,FOUT F1 BP A Figure 14 Fractional N PLL. FOUT FREF R BP A,Figure 12 PLL with dual modulus N counter. Analog Dialogue 52 07 July 2018 3,1 1 1 1 EVM,Phase Noise dBc Hz.
110 1 1 1 1,Figure 17 Phase error visualization,1k 10k 100k 1M 10M 100M. Frequency Hz,8 00 kHz 90 5043 dBc Hz,Figure 15 Integer N PLL in band phase noise. Phase Noise dBc Hz,Figure 18 Signal source analyzer plot. 140 VCO blocking specifications are very important in cellular systems that. need to account for the presence of strong transmissions If a receiver. signal is weak and if the VCO is too noisy then the nearby transmitter. 1k 10k 100k 1M 10M 100M, signal can mix down and drown out the wanted signal Figure 19 The. Frequency Hz illustration in Figure 19 demonstrates how the nearby transmitter 800 kHz. 8 00 kHz 105 6862 dBc Hz away transmitting at 25 dBm power could if the receiver VCO is noisy. Figure 16 Fractional N PLL in band phase noise swamp the wanted signal at 101 dBm These specifications form part of. a wireless communications standard The blocking specifications directly. For the majority of PLLs the in band noise is highly dependent on the N influence the performance requirement of the VCO. value and also on the PFD frequency Subtracting 20log N and 10log FPFD. from the flat portion of an in band phase noise measurement yields the. figure of merit FOM A common metric for choosing PLLs is to compare 25 dBm. the FOM Another factor that influences the in band noise is the 1 f noise Blocker. which is dependent on the output frequency of the device The FOM LO Phase. contribution and the 1 f noise together with the reference noise dominate. the in band noise of a PLL system,Narrow Band LO for 5G Communications 101 dBm.
Wanted Signal, For communication systems the chief specifications from the PLL per. spective are error vector magnitude EVM and VCO blocking specifications Figure 19 VCO noise blockers. EVM is similar in scope to integrated phase noise which considers the. noise contribution over a range of offsets For the 5G system listed earlier. the integration limits are quite wide starting at 1 kHz and continuing Voltage Controlled Oscillators VCOs. to 100 MHz EVM can be thought of as a percentage degradation of a The next PLL circuit element to be considered in our circuit is the voltage. perfectly modulated signal from its ideal point expressed as a percent controlled oscillator With VCOs a fundamental trade off between phase. age Figure 17 In a similar manner integrated phase noise integrates noise frequency coverage and power consumption is necessary The. the noise power at different offsets from the carrier and expresses this higher the quality factor Q of the oscillator the lower the VCO phase. can be configured to calculate the EVM integrated phase noise and rms noise is However higher Q circuits have narrower frequency ranges. phase error and jitter Modern signal source analyzers will also include Increasing the power supply will also lower the phase noise Looking at the. these numbers at the push of a button Figure 18 As modulation schemes Analog Devices family of VCOs the HMC507 covers a range of 6650 MHz. increase in density EVM becomes critical For 16 QAM the required min to 7650 MHz and the VCO noise at 100 kHz is approximately 115 dBc Hz. imum EVM according to ETSI specification 3GPP TS 36 104 is 12 5 For By contrast the HMC586 covers a full octave from 4000 MHz to 8000 MHz. 64 QAM the requirement is 8 However since EVM is comprised of various but has higher phase noise of 100 dBc Hz One strategy for minimizing. other nonideal parameters due to power amplifier distortion and unwanted phase noise in such VCOs is to increase the voltage tuning range of. mixer products the integrated noise in dBc is usually defined separately the VTUNE to the VCO up to 20 V or greater This increases PLL circuit. 4 Analog Dialogue 52 07 July 2018, complexity as most PLL charge pumps can only tune to 5 V so an active 60. filter using operational amplifiers is used to increase the tuning voltage of. the PLL circuit on its own,Multiband Integrated PLLs and VCOs 90. Phase Noise dBc Hz, Another strategy to increase frequency coverage without degrading VCO 100. phase noise is to use a multiband VCO in which overlapping frequency 110. ranges are used to cover an octave of frequency range and lower frequen. cies can be generated by using frequency dividers at the output of the VCO. Such a device is the ADF4356 which uses four main VCO cores each with 130. 256 overlapping frequency ranges The internal reference and feedback 140. frequency dividers are used by the device to choose the appropriate VCO. band a process known as VCO band select or autocalibration. 1k 10k 100k 1M 10M 100M, The wide tuning range of the multiband VCOs makes them suitable for Frequency Hz.
use in wideband instrumentation in which they generate a wide range of 1 00 MHz 115 8402 dBc Hz. frequencies The 39 bits of fractional N resolution also makes them ideal. Figure 21 Phase noise HMC704 plus HMC586, candidates for these precise frequency applications In instruments such as. vector network analyzers ultrafast switching speed is essential This can 1G. be achieved by using a very wide low pass filter bandwidth which tunes. to final frequency very quickly The automatic frequency calibration routine. can be bypassed in these applications by using a look up table with the 10M. ABS Frequency Error Hz, frequency values directly programmed for each frequency true single core 1M. wideband VCOs like the HMC733 can also be used with less complexity. For phase locked loop circuits the bandwidth of the low pass filter has a 10k. direct influence on the settling time of the system The low pass filter is 1k. the final element in our circuit If settling time is critical the loop bandwidth. should be increased to the maximum bandwidth permissible for achieving. stable lock and meeting phase noise and spurious frequency targets The 10. narrow band demands in a communications link mean the optimal band 1. width of the low pass filter for minimum integrated noise between 30 kHz. to 100 MHz is about 207 kHz Figure 20 using the HMC507 This provides 0 10 20 30 40 50 60 70 80 90 100. approximately 51 dBc of integrated noise and achieves frequency lock to Time sec. within 1 kHz error in about 51 s Figure 22 Figure 22 Frequency settling HMC704 plus HMC507. By contrast the wideband HMC586 covering from 4 GHz to 8 GHz 1G. achieves the optimum rms phase noise with a wider bandwidth closer. to 300 kHz bandwidth Figure 21 achieving 44 dBc of integrated noise. However it achieves frequency lock to the same specification in less than. ABS Frequency Error Hz, 27 s Figure 23 Correct part selection and the surrounding circuit design 1M. are all critical for achieving the best outcome for the application 100k. Phase Noise dBc Hz,0 10 20 30 40 50 60 70 80 90 100. frequency synthesizers in vector network analyzers VNA This article explains some of the building blocks of PLL circuits with references to each of these applications in turn to help guide the novice and PLL expert alike in navigating part selection and the trade offs inherent for each dif ferent application The article references the

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