A new architecture for PDP 11 Computer History Museum

A New Architecture For Pdp 11 Computer History Museum-Free PDF

  • Date:31 Jul 2020
  • Views:2
  • Downloads:0
  • Pages:19
  • Size:1.48 MB

Share Pdf : A New Architecture For Pdp 11 Computer History Museum

Download and Preview : A New Architecture For Pdp 11 Computer History Museum

Report CopyRight/DMCA Form For : A New Architecture For Pdp 11 Computer History Museum


658 Spring Joint Computer Conference 1970, 8 no larger model computer once a user outgrows a memory word length for the Model 20 is 16 bits. particular model although there are 32 and 48 bit instructions and 8. 9 high programming costs because users program and 16 bit data Other members of the family might. in machine language have up to 80 bit instructions with 8 16 32 and. 48 bit data The internal and preferred external, In developing a new computer the architecture character set was chosen to be 8 bit ASCII. should a t least solve the above problems Fortunately. in the late 1960 s integrated circuit semiconductor. technology became available so that newer computers Range and performance. could be designed which solve these problems a t low. cost Also by 1970 application experience was available Performance and function range extendability. to influence the design The new architecture should were the main design constraints in fact they were. thus lower programming cost while maintaining the the main reasons to build a new computer DEC. low hardware cost of mini computers already has 4 computer families that span a range. The DEC PDP 11 Model 20 is the first computer but are incompatible I n addition to the range the. of a computer family designed to span a range of func initial machine was constrained to fall within the. tions and performance The Model 20 is specifically small computer product line which means to have. discussed although design guidelines are presented about the same performance as a PDP 8 The initial. for other members of the family The Model 20 would machine outperforms the PDP 5 LINC and PDP 4. nominally be classified as a third generation integrated based families Performance of course is both a. circuits 16 bit word 1 central processor with eight function of the instruction set and the technology. 16 bit general registers using two s complement Here we re fundamentally only concerned with the. arithmetic and addressing up to 216 eight bit bytes of instruction set performance because faster hardware. primary memory core Though classified as a general will always increase performance for any family. register processor the operand accessing mechanism Unlike the earlier DEC families the PDP 11 had to. allows it to perform equally well as a O stack be designed so that new models with significantly. 1 general register and 2 memory to memory address more performance can be added to the family. computer The computer s components processor A rather obvious goal is maximum performance for. memories controls terminals are connected via a a given model Designs were programmed using bench. single switch called the Unibus marks and the results compared with both DEC and. The machine is described using the PMS and ISP potentially competitive machines Although the selling. notation of Bell and Newel1 1970 at different levels price was constrained to lie in the 5 000 to 10 000. The following descriptive sections correspond to the range it was realized that the decreasing cost of logic. levels external design constraints level the PMS would allow a more complex organization than earlier. level the way components are interconnected and DEC computers A design which could take advantage. allow information to flow the program level or ISP of medium and eventually large scale integration was. Instruction Set Processor the abstract machine an important consideration First it could make the. which interprets programs and finally the logical computer perform well and second it would extend. design level We omit a discussion of the circuit the computer family s life For these reasons a general. level the PDP 11 being constructed from TTL inte registers organization was chosen. grated circuits,Interrupt response,DESIGN CONSTRAINTS. Since the PDP 11 will be used for real time control. The principal design objective is yet to be tested applications it is important that devices can com. namely do users like the machine This will be tested municate with one another quickly i e the response. both in the market place and by the features that are time of a request should be short A multiple priority. emulated in newer machines it will indirectly be level nested interrupt mechanism was selected addi. tested by the life span of the PDP 11 and any offspring tional priority levels are provided by the physical. position of a device on the Unibus Software polling is. Word length, PDP 4 7 9 1 5 family PDP 5 8 8 S 8 I 8 L family LING. The most critical constraint word length defined PDP 8 LINC PDP I2 family and PDP 6 10 family The. by IBM was chosen to be a multiple of 8 bits The initial PDP I did not achieve family status. The DEC PDP 11 659, unnecessary because each device interrupt corresponds interpretation The processor memory connection is.
to a unique address asynchronous and therefore memory of any speed can. be connected The instruction set encourages the user. to write reentrant programs thus read only memory, Software can be used as part of primary memory to gain the. permanency and performance normally attributed to, The total system including software is of course the microprogramming In fact the Model 10 computer. main objective of the design Two techniques were which will not be further discussed has a 1024 word. used to aid programmability first benchmarks gave a read only memory and a 128 word read write memory. continuous indication as to how well the machine,interpreted programs second systems programmer. continually evaluated the design Their evaluation 0 nderstandability. considered what code the compiler would produce, how would the loader work ease of program reloc Understandability was perhaps the most funda. ability the use of a debugging program how the mental constraint or goal although it is now somewhat. compiler assembler and editor would be coded in less important to have a machine that can be quickly. effect other benchmarks how real time monitors understood by a novice computer user than it was a. would be written to use the various facilities and few years ago DEC s early success has been predi. present a clean interface to the users finally the ease cated on selling to an intelligent but inexperienced. of coding a program user Understandability though hard to measure is. an important goal because all potential users must. understand the computer A straightforward design, Modularity should simplify the systems programming task in the.
case of a compiler it should make translation par, Structural flexibility sometimes called modularity ticularly code generation easier. for a particular model was desired A flexible and, straightforward method for interconnecting components. had to be used because of varying user needs among PDP 11 STRUCTURE AT T H E PMS LEVEL. user classes and over time Users should have the, ability to configure an optimum system based on cost Introduction. performance and reliability both by interconnection. and when necessary constructing new components PDP 11 has the same organizational structure as. Since users build special hardware a computer should nearly all present day computers Figure 1 The. be easily interfaced As a by product of modularity primitive PMS components are the primary memory. computer components can be produced and stocked Mp which holds the programs while the central. rather than tailor made on order The physical struc processor Pc interprets them io controls Kio which. ture is almost identical to the PMS structure discussed manage data transfers between terminals T or second. in the following section thus reasonably large building ary memories Ms to primary memory Mp the. blocks are available to the user components outside the computer a t periphery X. either humans H or some external process e g,another computer the processor console T console. Microproyramm ins by which humans communicate with the computer. and observe its behavior and affect changes in its. A note on microprogramming is in order because of state and a switch S with its control K which. current interest in the firmware concept We believe allows all the other components to communicate with. microprogramming as we understand it Wilkes 1951 one another In the case of PDP 11 the central logical. can be a worthwhile technique as it applies to processor switch structure is implemented using a bus or chained. design For example microprogramming can probably switch S called the Unibus as shown in Figure 2. be used in larger computers when floating point data Each physical component has a switch for placing. operators are needed The IBM System 360 has messages on the bus or taking messages off the bus. made use of the technique for defining processors that The central control decides the next component to. interpret both the System 360 instruction set and, earlier family instruction sets e g 1401 1620 7090 A descriptive block diagram level Bell and Newell 1970 to.
I n the PDP 11 the basic instruction set is quite straight describe the relationship of the computer components processors. forward and does not necessitate microprogrammed memories switches controls links terminals and data operators. 660 Spring Joint Computer Conference 1970,h m n user. lines of the hierarchical structure common to present. processor day computers The single bus makes conventional. and other structures possible The message processes. in the structure which utilize S Unibus are,1 The central processor Pc requests that data. be read or written from or to primary memory,Mp for instructions and data The processor. secondary terminals calls a particular memory module by concur. rently specifying the module s address and the,address within the modules Depending on wheth. h u u n user,er the processor requests reading or writing.
other process,data is transmitted either from the memory to. the processor or vice versa, Convgntional block diagr 2 The central processor Pc controls the initializa. tion of secondary memory Ms and terminal T,activity The processor sets status bits in the. control associated with a particular Ms or T and,the device proceeds with the specified action. e g reading a card or punching a character into, Pc T conaole H paper tape Since some devices transfer data.
I vectors directly to primary memory the vector,xi0 fro periphery. control information i e the memory location,and length is given as initialization information. 3 Controls request the processor s attention in the. form of interrupts An interrupt request to the,processor has the effect of changing the state of. the processor thus the processor begins executing,a program associated with the interrupting. PUS Notatloo,process Note the interrupt process is only a.
capOnent x,signaling method and when the processor inter. ruption occurs the interruptee specifies a unique,address value to the processor The address is a. starting address for a program, 4 The central processor can control the transmission. of data between a control for T or Ms and,II attribute value v p l r s. either the processor or a primary memory for,Attribute my be omitted i f l t.
cam be inferred from d l r n s i o n a program controlled data transfers The device. attribute p l v l o g COIPOneDt number, signals for attention using the interrupt dialogue. attribute llvins coqolwnt ML and the central processor responds by managing. the data transmission in a fashion similar to,transmitting initialization information. computer H X X, Figure I Conventional block diagram and PMS diagram Pc Ki Kio. of PDP I1 np, use the bus for a message call The S Unibus differs. from most switches because any component can pom 1 Unibus control packaged w i t h Pc. municate with any other component, The types of messages in the PDP 11 are along the Figure 2 PDP 11 physical structwe PMS diagram.
The DEC PDP 11 661,Some device controls for T or Ms transfer data. directly to from primary memory without central,processor intervention In this mode the device. behaves similar to a processor a memory address,is specified and the data is transmitted between. the device and primary memory,The transfer of data between two controls e g a. secondary memory disk and say a terminal Figure 4 Conventional hierarchy compiiter structiire. display is not precluded provided the two use,compatible message formats.
components options In Figure 5 the Unibus charac, As we show more detail in the structure there are teristics are surpressed The detailed properties of the. of course more messages and more simultaneous switch are described in the logical design section. activity The above does not describe the shared, control and its associated switching which is typical of. Extensions to increase performance, a magnetic tape and magnetic disk secondary memory. systems A control for a DECtape memory Figure 3, The reader should note Figure 5 that the important. has an S DECtape bus for transmitting data between. limitations of the bus are a concurrency of one namely. only one dialogue can occur a t a given time and a. maximum transfer rate of one 16 bit word per 75 psec. 0 7 D E C t a p e giving a transfer rate of 21 3 megabits second While. the bus is not a limit for a uni processor structure it is. a limit for multiprocessor structures The bus also. Kio D E C t a p e, 3 imposes an artificial limit on the system performance.
when high speed devices e g T V cameras disks are,. A new architecture for mini computers The DEC PDP 11 by G BELL R CADY H McFARLAND B p imry memory words micro 8K mini 32 K midi 65 128 K pTOCeSSOT and memory cost 19YOkilodollars 5 5 10 10 20 Word PTOCesSOT length state bits 8 12 12 16 16 24 words 2 2 4 4 16 data types integers words boolean vectors vectors i e indexing double length floating point occasionally

Related Books